clk: Ingenic: Add RTC related clocks for Ingenic SoCs.

The RTC unit in the Ingenic SoCs has two clock sources, one
is from an external 32.768kHz clock, and the other is from an
external 24MHz/48MHz main clock that is divided by 512. The
choice of these two clocks is controlled by the ERCS bit in
the OPCR register. The RNG unit will also use this clock.

Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Link: https://lore.kernel.org/r/20200725051136.58220-4-zhouyanjie@wanyeetech.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c
index 6c5b8029cc8ab615e60241fc3ac01aa0e77a30e7..288e9694285b276d0594e7dea69470e0549e2e07 100644 (file)
--- a/drivers/clk/ingenic/jz4780-cgu.c
+++ b/drivers/clk/ingenic/jz4780-cgu.c
@@ -516,6 +516,18 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = {
                .gate = { CGU_REG_CLKGR0, 1 },
        },
 
+       [JZ4780_CLK_EXCLK_DIV512] = {
+               "exclk_div512", CGU_CLK_FIXDIV,
+               .parents = { JZ4780_CLK_EXCLK },
+               .fixdiv = { 512 },
+       },
+
+       [JZ4780_CLK_RTC] = {
+               "rtc_ercs", CGU_CLK_MUX | CGU_CLK_GATE,
+               .parents = { JZ4780_CLK_EXCLK_DIV512, JZ4780_CLK_RTCLK },
+               .mux = { CGU_REG_OPCR, 2, 1},
+       },
+
        /* Gate-only clocks */
 
        [JZ4780_CLK_NEMC] = {

diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c
index 453f3323cb99d4b8d475f566dc7e0ca58b06a05f..3cc37466ce6b29785d0a809012b6deb3a97f911c 100644 (file)
--- a/drivers/clk/ingenic/x1000-cgu.c
+++ b/drivers/clk/ingenic/x1000-cgu.c
@@ -278,6 +278,19 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
                .mux = { CGU_REG_SSICDR, 30, 1 },
        },
 
+       [X1000_CLK_EXCLK_DIV512] = {
+               "exclk_div512", CGU_CLK_FIXDIV,
+               .parents = { X1000_CLK_EXCLK },
+               .fixdiv = { 512 },
+       },
+
+       [X1000_CLK_RTC] = {
+               "rtc_ercs", CGU_CLK_MUX | CGU_CLK_GATE,
+               .parents = { X1000_CLK_EXCLK_DIV512, X1000_CLK_RTCLK },
+               .mux = { CGU_REG_OPCR, 2, 1},
+               .gate = { CGU_REG_CLKGR, 27 },
+       },
+
        /* Gate-only clocks */
 
        [X1000_CLK_EMC] = {

diff --git a/drivers/clk/ingenic/x1830-cgu.c b/drivers/clk/ingenic/x1830-cgu.c
index a1b2ff0ee48783130cc4efef197e9877c181d297..950aee243364edf193c5e4d152a943c7705cf55e 100644 (file)
--- a/drivers/clk/ingenic/x1830-cgu.c
+++ b/drivers/clk/ingenic/x1830-cgu.c
@@ -329,6 +329,19 @@ static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = {
                .mux = { CGU_REG_SSICDR, 29, 1 },
        },
 
+       [X1830_CLK_EXCLK_DIV512] = {
+               "exclk_div512", CGU_CLK_FIXDIV,
+               .parents = { X1830_CLK_EXCLK },
+               .fixdiv = { 512 },
+       },
+
+       [X1830_CLK_RTC] = {
+               "rtc_ercs", CGU_CLK_MUX | CGU_CLK_GATE,
+               .parents = { X1830_CLK_EXCLK_DIV512, X1830_CLK_RTCLK },
+               .mux = { CGU_REG_OPCR, 2, 1},
+               .gate = { CGU_REG_CLKGR0, 29 },
+       },
+
        /* Gate-only clocks */
 
        [X1830_CLK_EMC] = {