soundwire: qcom: add support for mmio soundwire master devices

Adds support for qcom soundwire devices with memory mapped IO registers.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20200905173905.16541-4-jonathan@marek.ca
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c
index 35517d1a7765fbd445ef704544bf4269364facec..4e66239c4417dd8dc825ce80deeffa26b9e7faba 100644 (file)
--- a/drivers/soundwire/qcom.c
+++ b/drivers/soundwire/qcom.c
@@ -34,6 +34,7 @@
 #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED          BIT(10)
 #define SWRM_INTERRUPT_MASK_ADDR                               0x204
 #define SWRM_INTERRUPT_CLEAR                                   0x208
+#define SWRM_INTERRUPT_CPU_EN                                  0x210
 #define SWRM_CMD_FIFO_WR_CMD                                   0x300
 #define SWRM_CMD_FIFO_RD_CMD                                   0x304
 #define SWRM_CMD_FIFO_CMD                                      0x308
@@ -87,6 +88,7 @@ struct qcom_swrm_ctrl {
        struct sdw_bus bus;
        struct device *dev;
        struct regmap *regmap;
+       void __iomem *mmio;
        struct completion *comp;
        struct work_struct slave_work;
        /* read/write lock */
@@ -151,6 +153,20 @@ static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl,
        return SDW_CMD_OK;
 }
 
+static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
+                                 u32 *val)
+{
+       *val = readl(ctrl->mmio + reg);
+       return SDW_CMD_OK;
+}
+
+static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg,
+                                  int val)
+{
+       writel(val, ctrl->mmio + reg);
+       return SDW_CMD_OK;
+}
+
 static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data,
                                     u8 dev_addr, u16 reg_addr)
 {
@@ -305,6 +321,12 @@ static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
        ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
                        SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK |
                        SWRM_COMP_CFG_ENABLE_MSK);
+
+       /* enable CPU IRQs */
+       if (ctrl->mmio) {
+               ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN,
+                               SWRM_INTERRUPT_STATUS_RMSK);
+       }
        return 0;
 }
 
@@ -756,8 +778,11 @@ static int qcom_swrm_probe(struct platform_device *pdev)
                if (!ctrl->regmap)
                        return -EINVAL;
        } else {
-               /* Only WCD based SoundWire controller is supported */
-               return -ENOTSUPP;
+               ctrl->reg_read = qcom_swrm_cpu_reg_read;
+               ctrl->reg_write = qcom_swrm_cpu_reg_write;
+               ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
+               if (IS_ERR(ctrl->mmio))
+                       return PTR_ERR(ctrl->mmio);
        }
 
        ctrl->irq = of_irq_get(dev->of_node, 0);