arm64: dts: imx8mp-msc-sm2s: correct i2c{1..6} pad drive strength

Adjust i2c drive strength based on latest Avnet BSP.

Signed-off-by: Ian Ray <ian.ray@gehealthcare.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi
index 61c2a63efc6dbfa4bc2f81d7264392fe8178279d..e794f05cf5aa5c3bad9ec30737a65190a19dc2bc 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi
@@ -602,38 +602,38 @@
 
        pinctrl_i2c1: i2c1grp {
                fsl,pins =
-                       <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL                0x400001c3>,
-                       <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA                0x400001c3>;
+                       <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL                0x400001e0>,
+                       <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA                0x400001e0>;
        };
 
        pinctrl_i2c2: i2c2grp {
                fsl,pins =
-                       <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL                0x400001c3>,
-                       <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA                0x400001c3>;
+                       <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL                0x400001e0>,
+                       <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA                0x400001e0>;
        };
 
        pinctrl_i2c3: i2c3grp {
                fsl,pins =
-                       <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL                0x400001c3>,
-                       <MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA                0x400001c3>;
+                       <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL                0x400001e0>,
+                       <MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA                0x400001e0>;
        };
 
        pinctrl_i2c4: i2c4grp {
                fsl,pins =
-                       <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL                0x400001c3>,
-                       <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA                0x400001c3>;
+                       <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL                0x400001e0>,
+                       <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA                0x400001e0>;
        };
 
        pinctrl_i2c5: i2c5grp {
                fsl,pins =
-                       <MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL                0x400001c3>,
-                       <MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA                0x400001c3>;
+                       <MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL                0x400001e0>,
+                       <MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA                0x400001e0>;
        };
 
        pinctrl_i2c6: i2c6grp {
                fsl,pins =
-                       <MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL               0x400001c3>,
-                       <MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA                0x400001c3>;
+                       <MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL               0x400001e0>,
+                       <MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA                0x400001e0>;
        };
 
        pinctrl_lcd0_backlight: lcd0-backlightgrp {