port@0 {
reg = <0>;
adv7533_in: endpoint {
- remote-endpoint = <&dsi0_out>;
+ remote-endpoint = <&mdss_dsi0_out>;
};
};
};
};
-&dsi0_out {
- data-lanes = <0 1 2 3>;
- remote-endpoint = <&adv7533_in>;
-};
-
&lpass {
status = "okay";
};
status = "okay";
};
+&mdss_dsi0_out {
+ data-lanes = <0 1 2 3>;
+ remote-endpoint = <&adv7533_in>;
+};
+
&mpss {
status = "okay";
vdda-supply = <&pm8916_l2>;
};
-&dsi0 {
+&mdss_dsi0 {
vdda-supply = <&pm8916_l2>;
vddio-supply = <&pm8916_l6>;
};
-&dsi_phy0 {
+&mdss_dsi0_phy {
vddio-supply = <&pm8916_l6>;
};
status = "okay";
};
-&dsi0 {
+&mdss {
+ status = "okay";
+};
+
+&mdss_dsi0 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mdss_default>;
pinctrl-1 = <&mdss_sleep>;
};
-&mdss {
- status = "okay";
-};
-
&pm8916_resin {
status = "okay";
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
};
-&dsi0 {
+&mdss_dsi0 {
panel@0 {
reg = <0>;
port {
panel_in: endpoint {
- remote-endpoint = <&dsi0_out>;
+ remote-endpoint = <&mdss_dsi0_out>;
};
};
};
};
-&dsi0_out {
+&mdss_dsi0_out {
data-lanes = <0 1>;
remote-endpoint = <&panel_in>;
};
status = "okay";
};
-/* Remove &dsi_phy0 from clocks to make sure that gcc probes with display disabled */
+/* Remove &mdss_dsi0_phy from clocks to make sure that gcc probes with display disabled */
&gcc {
clocks = <&xo_board>, <&sleep_clk>, <0>, <0>, <0>, <0>, <0>;
};
reg = <0x01800000 0x80000>;
clocks = <&xo_board>,
<&sleep_clk>,
- <&dsi_phy0 1>,
- <&dsi_phy0 0>,
+ <&mdss_dsi0_phy 1>,
+ <&mdss_dsi0_phy 0>,
<0>,
<0>,
<0>;
#size-cells = <1>;
ranges;
- mdp: display-controller@1a01000 {
+ mdss_mdp: display-controller@1a01000 {
compatible = "qcom,msm8916-mdp5", "qcom,mdp5";
reg = <0x01a01000 0x89000>;
reg-names = "mdp_phys";
port@0 {
reg = <0>;
- mdp5_intf1_out: endpoint {
- remote-endpoint = <&dsi0_in>;
+ mdss_mdp_intf1_out: endpoint {
+ remote-endpoint = <&mdss_dsi0_in>;
};
};
};
};
- dsi0: dsi@1a98000 {
+ mdss_dsi0: dsi@1a98000 {
compatible = "qcom,msm8916-dsi-ctrl",
"qcom,mdss-dsi-ctrl";
reg = <0x01a98000 0x25c>;
assigned-clocks = <&gcc BYTE0_CLK_SRC>,
<&gcc PCLK0_CLK_SRC>;
- assigned-clock-parents = <&dsi_phy0 0>,
- <&dsi_phy0 1>;
+ assigned-clock-parents = <&mdss_dsi0_phy 0>,
+ <&mdss_dsi0_phy 1>;
clocks = <&gcc GCC_MDSS_MDP_CLK>,
<&gcc GCC_MDSS_AHB_CLK>,
"byte",
"pixel",
"core";
- phys = <&dsi_phy0>;
+ phys = <&mdss_dsi0_phy>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
- dsi0_in: endpoint {
- remote-endpoint = <&mdp5_intf1_out>;
+ mdss_dsi0_in: endpoint {
+ remote-endpoint = <&mdss_mdp_intf1_out>;
};
};
port@1 {
reg = <1>;
- dsi0_out: endpoint {
+ mdss_dsi0_out: endpoint {
};
};
};
};
- dsi_phy0: phy@1a98300 {
+ mdss_dsi0_phy: phy@1a98300 {
compatible = "qcom,dsi-phy-28nm-lp";
reg = <0x01a98300 0xd4>,
<0x01a98500 0x280>,
#include "msm8939.dtsi"
#include "pm8916.dtsi"
-&dsi0 {
+&mdss_dsi0 {
vdda-supply = <&pm8916_l2>;
vddio-supply = <&pm8916_l6>;
};
-&dsi1 {
- vdda-supply = <&pm8916_l2>;
+&mdss_dsi0_phy {
vddio-supply = <&pm8916_l6>;
};
-&dsi_phy0 {
+&mdss_dsi1 {
+ vdda-supply = <&pm8916_l2>;
vddio-supply = <&pm8916_l6>;
};
-&dsi_phy1 {
+&mdss_dsi1_phy {
vddio-supply = <&pm8916_l6>;
};
reg = <0x01800000 0x80000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&sleep_clk>,
- <&dsi_phy0 1>,
- <&dsi_phy0 0>,
+ <&mdss_dsi0_phy 1>,
+ <&mdss_dsi0_phy 0>,
<0>,
<0>,
<0>;
status = "disabled";
- mdp: display-controller@1a01000 {
+ mdss_mdp: display-controller@1a01000 {
compatible = "qcom,mdp5";
reg = <0x01a01000 0x89000>;
reg-names = "mdp_phys";
port@0 {
reg = <0>;
- mdp5_intf1_out: endpoint {
- remote-endpoint = <&dsi0_in>;
+ mdss_mdp_intf1_out: endpoint {
+ remote-endpoint = <&mdss_dsi0_in>;
};
};
port@1 {
reg = <1>;
- mdp5_intf2_out: endpoint {
- remote-endpoint = <&dsi1_in>;
+ mdss_mdp_intf2_out: endpoint {
+ remote-endpoint = <&mdss_dsi1_in>;
};
};
};
};
- dsi0: dsi@1a98000 {
+ mdss_dsi0: dsi@1a98000 {
compatible = "qcom,msm8916-dsi-ctrl",
"qcom,mdss-dsi-ctrl";
reg = <0x01a98000 0x25c>;
"core";
assigned-clocks = <&gcc BYTE0_CLK_SRC>,
<&gcc PCLK0_CLK_SRC>;
- assigned-clock-parents = <&dsi_phy0 0>,
- <&dsi_phy0 1>;
+ assigned-clock-parents = <&mdss_dsi0_phy 0>,
+ <&mdss_dsi0_phy 1>;
- phys = <&dsi_phy0>;
+ phys = <&mdss_dsi0_phy>;
status = "disabled";
#address-cells = <1>;
port@0 {
reg = <0>;
- dsi0_in: endpoint {
- remote-endpoint = <&mdp5_intf1_out>;
+ mdss_dsi0_in: endpoint {
+ remote-endpoint = <&mdss_mdp_intf1_out>;
};
};
port@1 {
reg = <1>;
- dsi0_out: endpoint {
+ mdss_dsi0_out: endpoint {
};
};
};
};
- dsi_phy0: phy@1a98300 {
+ mdss_dsi0_phy: phy@1a98300 {
compatible = "qcom,dsi-phy-28nm-lp";
reg = <0x01a98300 0xd4>,
<0x01a98500 0x280>,
status = "disabled";
};
- dsi1: dsi@1aa0000 {
+ mdss_dsi1: dsi@1aa0000 {
compatible = "qcom,msm8916-dsi-ctrl",
"qcom,mdss-dsi-ctrl";
reg = <0x01aa0000 0x25c>;
"core";
assigned-clocks = <&gcc BYTE1_CLK_SRC>,
<&gcc PCLK1_CLK_SRC>;
- assigned-clock-parents = <&dsi_phy0 0>,
- <&dsi_phy0 1>;
- phys = <&dsi_phy1>;
+ assigned-clock-parents = <&mdss_dsi0_phy 0>,
+ <&mdss_dsi0_phy 1>;
+ phys = <&mdss_dsi1_phy>;
status = "disabled";
ports {
port@0 {
reg = <0>;
- dsi1_in: endpoint {
- remote-endpoint = <&mdp5_intf2_out>;
+ mdss_dsi1_in: endpoint {
+ remote-endpoint = <&mdss_mdp_intf2_out>;
};
};
port@1 {
reg = <1>;
- dsi1_out: endpoint {
+ mdss_dsi1_out: endpoint {
};
};
};
};
- dsi_phy1: phy@1aa0300 {
+ mdss_dsi1_phy: phy@1aa0300 {
compatible = "qcom,dsi-phy-28nm-lp";
reg = <0x01aa0300 0xd4>,
<0x01aa0500 0x280>,