riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC

Add the quad spi controller node for the StarFive JH7110 SoC.

Co-developed-by: Ziv Xu <ziv.xu@starfivetech.com>
Signed-off-by: Ziv Xu <ziv.xu@starfivetech.com>
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index f874d31006a60dd1932117e60de13cb70f18bd7f..d2f3b9eb859bdf1506d7494b60316f19ef168a76 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -185,6 +185,42 @@
        status = "okay";
 };
 
+&qspi {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       status = "okay";
+
+       nor_flash: flash@0 {
+               compatible = "jedec,spi-nor";
+               reg = <0>;
+               cdns,read-delay = <5>;
+               spi-max-frequency = <12000000>;
+               cdns,tshsl-ns = <1>;
+               cdns,tsd2d-ns = <1>;
+               cdns,tchsh-ns = <1>;
+               cdns,tslch-ns = <1>;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       spl@0 {
+                               reg = <0x0 0x80000>;
+                       };
+                       uboot-env@f0000 {
+                               reg = <0xf0000 0x10000>;
+                       };
+                       uboot@100000 {
+                               reg = <0x100000 0x400000>;
+                       };
+                       reserved-data@600000 {
+                               reg = <0x600000 0x1000000>;
+                       };
+               };
+       };
+};
+
 &spi0 {
        pinctrl-names = "default";
        pinctrl-0 = <&spi0_pins>;

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 05f843b8ca0343d9da94086062714cd035764bcb..a608433200e88b28ec8f3e15d15652d8bdcb40b1 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -676,6 +676,25 @@
                        status = "disabled";
                };
 
+               qspi: spi@13010000 {
+                       compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
+                       reg = <0x0 0x13010000 0x0 0x10000>,
+                             <0x0 0x21000000 0x0 0x400000>;
+                       interrupts = <25>;
+                       clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
+                                <&syscrg JH7110_SYSCLK_QSPI_AHB>,
+                                <&syscrg JH7110_SYSCLK_QSPI_APB>;
+                       clock-names = "ref", "ahb", "apb";
+                       resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
+                                <&syscrg JH7110_SYSRST_QSPI_AHB>,
+                                <&syscrg JH7110_SYSRST_QSPI_REF>;
+                       reset-names = "qspi", "qspi-ocp", "rstc_ref";
+                       cdns,fifo-depth = <256>;
+                       cdns,fifo-width = <4>;
+                       cdns,trigger-address = <0x0>;
+                       status = "disabled";
+               };
+
                spi3: spi@12070000 {
                        compatible = "arm,pl022", "arm,primecell";
                        reg = <0x0 0x12070000 0x0 0x10000>;