x86/cpu, kvm: Move X86_FEATURE_LFENCE_RDTSC to its native leaf

The LFENCE always serializing feature bit was defined as scattered
LFENCE_RDTSC and its native leaf bit position open-coded for KVM.  Add
it to its newly added CPUID leaf 0x80000021 EAX proper.  With
LFENCE_RDTSC in its proper place, the kernel's set_cpu_cap() will
effectively synthesize the feature for KVM going forward.

Also, DE_CFG[1] doesn't need to be set on such CPUs anymore.

  [ bp: Massage and merge diff from Sean. ]

Signed-off-by: Kim Phillips <kim.phillips@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Acked-by: Sean Christopherson <seanjc@google.com>
Link: https://lore.kernel.org/r/20230124163319.2277355-5-kim.phillips@amd.com

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 1b2d40a96b9784cd45ef42b50deb162968f1e8c5..901128ed4c7a5d47ef1e97d2c1910e17f0bd339a 100644 (file)
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -97,7 +97,7 @@
 #define X86_FEATURE_SYSENTER32         ( 3*32+15) /* "" sysenter in IA32 userspace */
 #define X86_FEATURE_REP_GOOD           ( 3*32+16) /* REP microcode works well */
 #define X86_FEATURE_AMD_LBR_V2         ( 3*32+17) /* AMD Last Branch Record Extension Version 2 */
-#define X86_FEATURE_LFENCE_RDTSC       ( 3*32+18) /* "" LFENCE synchronizes RDTSC */
+/* FREE, was #define X86_FEATURE_LFENCE_RDTSC          ( 3*32+18) "" LFENCE synchronizes RDTSC */
 #define X86_FEATURE_ACC_POWER          ( 3*32+19) /* AMD Accumulated Power Mechanism */
 #define X86_FEATURE_NOPL               ( 3*32+20) /* The NOPL (0F 1F) instructions */
 #define X86_FEATURE_ALWAYS             ( 3*32+21) /* "" Always-present feature */
@@ -429,6 +429,7 @@
 
 /* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */
 #define X86_FEATURE_NO_NESTED_DATA_BP  (20*32+ 0) /* "" No Nested Data Breakpoints */
+#define X86_FEATURE_LFENCE_RDTSC       (20*32+ 2) /* "" LFENCE always serializing / synchronizes RDTSC */
 
 /*
  * BUG word(s)

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index f769d6d08b433a53b3c3bf8f03a87dd4249af76d..208c2ce8598a8aba073955def3810f608cdace2a 100644 (file)
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -956,7 +956,7 @@ static void init_amd(struct cpuinfo_x86 *c)
 
        init_amd_cacheinfo(c);
 
-       if (cpu_has(c, X86_FEATURE_XMM2)) {
+       if (!cpu_has(c, X86_FEATURE_LFENCE_RDTSC) && cpu_has(c, X86_FEATURE_XMM2)) {
                /*
                 * Use LFENCE for execution serialization.  On families which
                 * don't have that MSR, LFENCE is already serializing.

diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index aa3a6dc74e95cea9afe21b4242439068a9856e4d..12455dc5afe52e6cf9127c5e7fd20ae41af2c000 100644 (file)
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -742,12 +742,22 @@ void kvm_set_cpu_caps(void)
                F(SME_COHERENT));
 
        kvm_cpu_cap_mask(CPUID_8000_0021_EAX,
-               F(NO_NESTED_DATA_BP) |
-               BIT(2) /* LFENCE Always serializing */ | 0 /* SmmPgCfgLock */ |
+               F(NO_NESTED_DATA_BP) | F(LFENCE_RDTSC) | 0 /* SmmPgCfgLock */ |
                BIT(6) /* NULL_SEL_CLR_BASE */ | 0 /* PrefetchCtlMsr */
        );
+
+       /*
+        * Synthesize "LFENCE is serializing" into the AMD-defined entry in
+        * KVM's supported CPUID if the feature is reported as supported by the
+        * kernel.  LFENCE_RDTSC was a Linux-defined synthetic feature long
+        * before AMD joined the bandwagon, e.g. LFENCE is serializing on most
+        * CPUs that support SSE2.  On CPUs that don't support AMD's leaf,
+        * kvm_cpu_cap_mask() will unfortunately drop the flag due to ANDing
+        * the mask with the raw host CPUID, and reporting support in AMD's
+        * leaf can make it easier for userspace to detect the feature.
+        */
        if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC))
-               kvm_cpu_caps[CPUID_8000_0021_EAX] |= BIT(2) /* LFENCE Always serializing */;
+               kvm_cpu_cap_set(X86_FEATURE_LFENCE_RDTSC);
        if (!static_cpu_has_bug(X86_BUG_NULL_SEG))
                kvm_cpu_caps[CPUID_8000_0021_EAX] |= BIT(6) /* NULL_SEL_CLR_BASE */;
        kvm_cpu_caps[CPUID_8000_0021_EAX] |= BIT(9) /* NO_SMM_CTL_MSR */;