wifi: rtw89: pci: enable CLK_REQ, ASPM, L1 and L1ss for 8852c

8852CE controls CLKREQ, ASPM L1, L1ss via wifi registers
instead, so change them accordingly.

Signed-off-by: Chin-Yen Lee <timlee@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220819064811.37700-5-pkshih@realtek.com

diff --git a/drivers/net/wireless/realtek/rtw89/pci.c b/drivers/net/wireless/realtek/rtw89/pci.c
index 650cbd7aff41f39d489de5a36b9140d56fff4df8..24aefd4041be76e5f6583d80353c86d31865bfc6 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/pci.c
+++ b/drivers/net/wireless/realtek/rtw89/pci.c
@@ -3293,6 +3293,7 @@ static int rtw89_pci_filter_out(struct rtw89_dev *rtwdev)
 
 static void rtw89_pci_clkreq_set(struct rtw89_dev *rtwdev, bool enable)
 {
+       enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
        int ret;
 
        if (rtw89_pci_disable_clkreq)
@@ -3303,19 +3304,33 @@ static void rtw89_pci_clkreq_set(struct rtw89_dev *rtwdev, bool enable)
        if (ret)
                rtw89_err(rtwdev, "failed to set CLKREQ Delay\n");
 
-       if (enable)
-               ret = rtw89_pci_config_byte_set(rtwdev, RTW89_PCIE_L1_CTRL,
-                                               RTW89_PCIE_BIT_CLK);
-       else
-               ret = rtw89_pci_config_byte_clr(rtwdev, RTW89_PCIE_L1_CTRL,
-                                               RTW89_PCIE_BIT_CLK);
-       if (ret)
-               rtw89_err(rtwdev, "failed to %s CLKREQ_L1, ret=%d",
-                         enable ? "set" : "unset", ret);
+       if (chip_id == RTL8852A) {
+               if (enable)
+                       ret = rtw89_pci_config_byte_set(rtwdev,
+                                                       RTW89_PCIE_L1_CTRL,
+                                                       RTW89_PCIE_BIT_CLK);
+               else
+                       ret = rtw89_pci_config_byte_clr(rtwdev,
+                                                       RTW89_PCIE_L1_CTRL,
+                                                       RTW89_PCIE_BIT_CLK);
+               if (ret)
+                       rtw89_err(rtwdev, "failed to %s CLKREQ_L1, ret=%d",
+                                 enable ? "set" : "unset", ret);
+       } else if (chip_id == RTL8852C) {
+               rtw89_write32_set(rtwdev, R_AX_PCIE_LAT_CTRL,
+                                 B_AX_CLK_REQ_SEL_OPT | B_AX_CLK_REQ_SEL);
+               if (enable)
+                       rtw89_write32_set(rtwdev, R_AX_L1_CLK_CTRL,
+                                         B_AX_CLK_REQ_N);
+               else
+                       rtw89_write32_clr(rtwdev, R_AX_L1_CLK_CTRL,
+                                         B_AX_CLK_REQ_N);
+       }
 }
 
 static void rtw89_pci_aspm_set(struct rtw89_dev *rtwdev, bool enable)
 {
+       enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
        u8 value = 0;
        int ret;
 
@@ -3334,12 +3349,23 @@ static void rtw89_pci_aspm_set(struct rtw89_dev *rtwdev, bool enable)
        if (ret)
                rtw89_err(rtwdev, "failed to read ASPM Delay\n");
 
-       if (enable)
-               ret = rtw89_pci_config_byte_set(rtwdev, RTW89_PCIE_L1_CTRL,
-                                               RTW89_PCIE_BIT_L1);
-       else
-               ret = rtw89_pci_config_byte_clr(rtwdev, RTW89_PCIE_L1_CTRL,
-                                               RTW89_PCIE_BIT_L1);
+       if (chip_id == RTL8852A || chip_id == RTL8852B) {
+               if (enable)
+                       ret = rtw89_pci_config_byte_set(rtwdev,
+                                                       RTW89_PCIE_L1_CTRL,
+                                                       RTW89_PCIE_BIT_L1);
+               else
+                       ret = rtw89_pci_config_byte_clr(rtwdev,
+                                                       RTW89_PCIE_L1_CTRL,
+                                                       RTW89_PCIE_BIT_L1);
+       } else if (chip_id == RTL8852C) {
+               if (enable)
+                       rtw89_write32_set(rtwdev, R_AX_PCIE_MIX_CFG_V1,
+                                         B_AX_ASPM_CTRL_L1);
+               else
+                       rtw89_write32_clr(rtwdev, R_AX_PCIE_MIX_CFG_V1,
+                                         B_AX_ASPM_CTRL_L1);
+       }
        if (ret)
                rtw89_err(rtwdev, "failed to %s ASPM L1, ret=%d",
                          enable ? "set" : "unset", ret);
@@ -3400,17 +3426,34 @@ static void rtw89_pci_link_cfg(struct rtw89_dev *rtwdev)
 
 static void rtw89_pci_l1ss_set(struct rtw89_dev *rtwdev, bool enable)
 {
+       enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
        int ret;
 
-       if (enable)
-               ret = rtw89_pci_config_byte_set(rtwdev, RTW89_PCIE_TIMER_CTRL,
-                                               RTW89_PCIE_BIT_L1SUB);
-       else
-               ret = rtw89_pci_config_byte_clr(rtwdev, RTW89_PCIE_TIMER_CTRL,
-                                               RTW89_PCIE_BIT_L1SUB);
-       if (ret)
-               rtw89_err(rtwdev, "failed to %s L1SS, ret=%d",
-                         enable ? "set" : "unset", ret);
+       if (chip_id == RTL8852A || chip_id == RTL8852B) {
+               if (enable)
+                       ret = rtw89_pci_config_byte_set(rtwdev,
+                                                       RTW89_PCIE_TIMER_CTRL,
+                                                       RTW89_PCIE_BIT_L1SUB);
+               else
+                       ret = rtw89_pci_config_byte_clr(rtwdev,
+                                                       RTW89_PCIE_TIMER_CTRL,
+                                                       RTW89_PCIE_BIT_L1SUB);
+               if (ret)
+                       rtw89_err(rtwdev, "failed to %s L1SS, ret=%d",
+                                 enable ? "set" : "unset", ret);
+       } else if (chip_id == RTL8852C) {
+               ret = rtw89_pci_config_byte_clr(rtwdev, RTW89_PCIE_L1SS_STS_V1,
+                                               RTW89_PCIE_BIT_ASPM_L11 |
+                                               RTW89_PCIE_BIT_PCI_L11);
+               if (ret)
+                       rtw89_warn(rtwdev, "failed to unset ASPM L1.1, ret=%d", ret);
+               if (enable)
+                       rtw89_write32_clr(rtwdev, R_AX_PCIE_MIX_CFG_V1,
+                                         B_AX_L1SUB_DISABLE);
+               else
+                       rtw89_write32_set(rtwdev, R_AX_PCIE_MIX_CFG_V1,
+                                         B_AX_L1SUB_DISABLE);
+       }
 }
 
 static void rtw89_pci_l1ss_cfg(struct rtw89_dev *rtwdev)

diff --git a/drivers/net/wireless/realtek/rtw89/pci.h b/drivers/net/wireless/realtek/rtw89/pci.h
index e80380271cd353fd51000e0cb5baa53dc5ee3aa9..63dc6d4db60224160f22ccfd67f9aaa455badf76 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/pci.h
+++ b/drivers/net/wireless/realtek/rtw89/pci.h
@@ -62,9 +62,16 @@
 #define B_AX_REQ_ENTR_L1               BIT(8)
 #define B_AX_L1SUB_DISABLE             BIT(0)
 
+#define R_AX_L1_CLK_CTRL               0x3010
+#define B_AX_CLK_REQ_N                 BIT(1)
+
 #define R_AX_PCIE_BG_CLR               0x303C
 #define B_AX_BG_CLR_ASYNC_M3           BIT(4)
 
+#define R_AX_PCIE_LAT_CTRL             0x3044
+#define B_AX_CLK_REQ_SEL_OPT           BIT(1)
+#define B_AX_CLK_REQ_SEL               BIT(0)
+
 #define R_AX_PCIE_IO_RCY_M1 0x3100
 #define B_AX_PCIE_IO_RCY_P_M1 BIT(5)
 #define B_AX_PCIE_IO_RCY_WDT_P_M1 BIT(4)
@@ -531,6 +538,11 @@
 #define RTW89_PCIE_GEN2_SPEED          0x02
 #define RTW89_PCIE_PHY_RATE            0x82
 #define RTW89_PCIE_PHY_RATE_MASK       GENMASK(1, 0)
+#define RTW89_PCIE_L1SS_STS_V1         0x0168
+#define RTW89_PCIE_BIT_ASPM_L11                BIT(3)
+#define RTW89_PCIE_BIT_ASPM_L12                BIT(2)
+#define RTW89_PCIE_BIT_PCI_L11         BIT(1)
+#define RTW89_PCIE_BIT_PCI_L12         BIT(0)
 #define RTW89_PCIE_ASPM_CTRL           0x070F
 #define RTW89_L1DLY_MASK               GENMASK(5, 3)
 #define RTW89_L0DLY_MASK               GENMASK(2, 0)