drm/xe/rtp: Support multiple actions per entry

Just like there is support for multiple rules per entry in an rtp table,
also support multiple actions. This makes it easier to add support for
workarounds that need to change multiple registers. It also makes it
slightly more readable as now the action part resembles the rule part.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
index 469b274198b19084fa0bd8a3a212caeca861e2cf..a34617a642ec67b453f65594535470391f296e2a 100644 (file)
--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
@@ -26,35 +26,32 @@ static bool match_not_render(const struct xe_gt *gt,
 static const struct xe_rtp_entry register_whitelist[] = {
        { XE_RTP_NAME("WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865"),
          XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
-         XE_WHITELIST_REGISTER(PS_INVOCATION_COUNT,
-                               RING_FORCE_TO_NONPRIV_ACCESS_RD |
-                               RING_FORCE_TO_NONPRIV_RANGE_4)
+         XE_RTP_ACTIONS(WHITELIST(PS_INVOCATION_COUNT,
+                                  RING_FORCE_TO_NONPRIV_ACCESS_RD |
+                                  RING_FORCE_TO_NONPRIV_RANGE_4))
        },
        { XE_RTP_NAME("1508744258, 14012131227, 1808121037"),
          XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
-         XE_WHITELIST_REGISTER(GEN7_COMMON_SLICE_CHICKEN1, 0)
+         XE_RTP_ACTIONS(WHITELIST(GEN7_COMMON_SLICE_CHICKEN1, 0))
        },
        { XE_RTP_NAME("1806527549"),
          XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
-         XE_WHITELIST_REGISTER(HIZ_CHICKEN, 0)
+         XE_RTP_ACTIONS(WHITELIST(HIZ_CHICKEN, 0))
        },
        { XE_RTP_NAME("allow_read_ctx_timestamp"),
          XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260), FUNC(match_not_render)),
-         XE_WHITELIST_REGISTER(RING_CTX_TIMESTAMP(0),
+         XE_RTP_ACTIONS(WHITELIST(RING_CTX_TIMESTAMP(0),
                                RING_FORCE_TO_NONPRIV_ACCESS_RD,
-                               XE_RTP_ACTION_FLAG(ENGINE_BASE))
+                               XE_RTP_ACTION_FLAG(ENGINE_BASE)))
        },
-       { XE_RTP_NAME("16014440446_part_1"),
+       { XE_RTP_NAME("16014440446"),
          XE_RTP_RULES(PLATFORM(PVC)),
-         XE_WHITELIST_REGISTER(_MMIO(0x4400),
-                               RING_FORCE_TO_NONPRIV_DENY |
-                               RING_FORCE_TO_NONPRIV_RANGE_64)
-       },
-       { XE_RTP_NAME("16014440446_part_2"),
-         XE_RTP_RULES(PLATFORM(PVC)),
-         XE_WHITELIST_REGISTER(_MMIO(0x4500),
-                               RING_FORCE_TO_NONPRIV_DENY |
-                               RING_FORCE_TO_NONPRIV_RANGE_64)
+         XE_RTP_ACTIONS(WHITELIST(_MMIO(0x4400),
+                                  RING_FORCE_TO_NONPRIV_DENY |
+                                  RING_FORCE_TO_NONPRIV_RANGE_64),
+                        WHITELIST(_MMIO(0x4500),
+                                  RING_FORCE_TO_NONPRIV_DENY |
+                                  RING_FORCE_TO_NONPRIV_RANGE_64))
        },
        {}
 };

diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c
index 11135db1a19d8589028997b21a3a8d73773b4cb2..5b1316b588d8117d4582cfcdd3faeb7fe8230857 100644 (file)
--- a/drivers/gpu/drm/xe/xe_rtp.c
+++ b/drivers/gpu/drm/xe/xe_rtp.c
@@ -86,18 +86,18 @@ static bool rule_matches(struct xe_gt *gt,
        return true;
 }
 
-static void rtp_add_sr_entry(const struct xe_rtp_entry *entry,
+static void rtp_add_sr_entry(const struct xe_rtp_action *action,
                             struct xe_gt *gt,
                             u32 mmio_base,
                             struct xe_reg_sr *sr)
 {
-       u32 reg = entry->action.reg + mmio_base;
+       u32 reg = action->reg + mmio_base;
        struct xe_reg_sr_entry sr_entry = {
-               .clr_bits = entry->action.clr_bits,
-               .set_bits = entry->action.set_bits,
-               .read_mask = entry->action.read_mask,
-               .masked_reg = entry->action.flags & XE_RTP_ACTION_FLAG_MASKED_REG,
-               .reg_type = entry->action.reg_type,
+               .clr_bits = action->clr_bits,
+               .set_bits = action->set_bits,
+               .read_mask = action->read_mask,
+               .masked_reg = action->flags & XE_RTP_ACTION_FLAG_MASKED_REG,
+               .reg_type = action->reg_type,
        };
 
        xe_reg_sr_add(sr, reg, &sr_entry);
@@ -106,18 +106,22 @@ static void rtp_add_sr_entry(const struct xe_rtp_entry *entry,
 static void rtp_process_one(const struct xe_rtp_entry *entry, struct xe_gt *gt,
                            struct xe_hw_engine *hwe, struct xe_reg_sr *sr)
 {
+       const struct xe_rtp_action *action;
        u32 mmio_base;
+       unsigned int i;
 
        if (!rule_matches(gt, hwe, entry))
                return;
 
-       if ((entry->flags & XE_RTP_ENTRY_FLAG_FOREACH_ENGINE) ||
-           (entry->action.flags & XE_RTP_ACTION_FLAG_ENGINE_BASE))
-               mmio_base = hwe->mmio_base;
-       else
-               mmio_base = 0;
+       for (action = &entry->actions[0]; i < entry->n_actions; action++, i++) {
+               if ((entry->flags & XE_RTP_ENTRY_FLAG_FOREACH_ENGINE) ||
+                   (action->flags & XE_RTP_ACTION_FLAG_ENGINE_BASE))
+                       mmio_base = hwe->mmio_base;
+               else
+                       mmio_base = 0;
 
-       rtp_add_sr_entry(entry, gt, mmio_base, sr);
+               rtp_add_sr_entry(action, gt, mmio_base, sr);
+       }
 }
 
 /**

diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
index 5d9ad31b0048825ddf71c95677fe6f7fd1b0e347..1ac3fd1c0734d51f0ab3be2973f2a4d3ecf861ff 100644 (file)
--- a/drivers/gpu/drm/xe/xe_rtp.h
+++ b/drivers/gpu/drm/xe/xe_rtp.h
@@ -44,10 +44,8 @@ struct xe_reg_sr;
 #define CALL_FOR_EACH(MACRO_, x, ...)                                          \
        _CALL_FOR_EACH(COUNT_ARGS(x, ##__VA_ARGS__), MACRO_, x, ##__VA_ARGS__)
 
-#define _XE_RTP_REG(x_)        (x_),                                           \
-                       .reg_type = XE_RTP_REG_REGULAR
-#define _XE_RTP_MCR_REG(x_) (x_),                                      \
-                           .reg_type = XE_RTP_REG_MCR
+#define _XE_RTP_REG(x_)        (x_), XE_RTP_REG_REGULAR
+#define _XE_RTP_MCR_REG(x_) (x_), XE_RTP_REG_MCR
 
 /*
  * Helper macros for concatenating prefix - do not use them directly outside
@@ -56,6 +54,7 @@ struct xe_reg_sr;
 #define __ADD_XE_RTP_ENTRY_FLAG_PREFIX(x) CONCATENATE(XE_RTP_ENTRY_FLAG_, x) |
 #define __ADD_XE_RTP_ACTION_FLAG_PREFIX(x) CONCATENATE(XE_RTP_ACTION_FLAG_, x) |
 #define __ADD_XE_RTP_RULE_PREFIX(x) CONCATENATE(XE_RTP_RULE_, x) ,
+#define __ADD_XE_RTP_ACTION_PREFIX(x) CONCATENATE(XE_RTP_ACTION_, x) ,
 
 /*
  * Macros to encode rules to match against platform, IP version, stepping, etc.
@@ -197,8 +196,10 @@ struct xe_reg_sr;
        { .match_type = XE_RTP_MATCH_DISCRETE }
 
 /**
- * XE_RTP_WR - Helper to write a value to the register, overriding all the bits
+ * XE_RTP_ACTION_WR - Helper to write a value to the register, overriding all
+ *                    the bits
  * @reg_: Register
+ * @reg_type_: Register type - automatically expanded by MCR_REG/_MMIO
  * @val_: Value to set
  * @...: Additional fields to override in the struct xe_rtp_action entry
  *
@@ -206,13 +207,15 @@ struct xe_reg_sr;
  *
  *     REGNAME = VALUE
  */
-#define XE_RTP_WR(reg_, val_, ...)                                             \
-       .action = { .reg = reg_, .clr_bits = ~0u, .set_bits = (val_),           \
-                   .read_mask = (~0u), ##__VA_ARGS__ }
+#define XE_RTP_ACTION_WR(reg_, reg_type_, val_, ...)                           \
+       { .reg = (reg_), .reg_type = (reg_type_),                               \
+         .clr_bits = ~0u, .set_bits = (val_),                                  \
+         .read_mask = (~0u), ##__VA_ARGS__ }
 
 /**
- * XE_RTP_SET - Set bits from @val_ in the register.
+ * XE_RTP_ACTION_SET - Set bits from @val_ in the register.
  * @reg_: Register
+ * @reg_type_: Register type - automatically expanded by MCR_REG/_MMIO
  * @val_: Bits to set in the register
  * @...: Additional fields to override in the struct xe_rtp_action entry
  *
@@ -223,13 +226,15 @@ struct xe_reg_sr;
  *     REGNAME[2] = 1
  *     REGNAME[5] = 1
  */
-#define XE_RTP_SET(reg_, val_, ...)                                            \
-       .action = { .reg = reg_, .clr_bits = (val_), .set_bits = (val_),        \
-                   .read_mask = (val_), ##__VA_ARGS__ }
+#define XE_RTP_ACTION_SET(reg_, reg_type_, val_, ...)                          \
+       { .reg = (reg_), .reg_type = (reg_type_),                               \
+         .clr_bits = (val_), .set_bits = (val_),                               \
+         .read_mask = (val_), ##__VA_ARGS__ }
 
 /**
- * XE_RTP_CLR: Clear bits from @val_ in the register.
+ * XE_RTP_ACTION_CLR: Clear bits from @val_ in the register.
  * @reg_: Register
+ * @reg_type_: Register type - automatically expanded by MCR_REG/_MMIO
  * @val_: Bits to clear in the register
  * @...: Additional fields to override in the struct xe_rtp_action entry
  *
@@ -240,13 +245,15 @@ struct xe_reg_sr;
  *     REGNAME[2] = 0
  *     REGNAME[5] = 0
  */
-#define XE_RTP_CLR(reg_, val_, ...)                                            \
-       .action = { .reg = reg_, .clr_bits = (val_), .set_bits = 0,             \
-                   .read_mask = (val_), ##__VA_ARGS__ }
+#define XE_RTP_ACTION_CLR(reg_, reg_type_, val_, ...)                          \
+       { .reg = (reg_), .reg_type = (reg_type_),                               \
+         .clr_bits = (val_), .set_bits = 0,                                    \
+         .read_mask = (val_), ##__VA_ARGS__ }
 
 /**
- * XE_RTP_FIELD_SET: Set a bit range, defined by @mask_bits_, to the value in
+ * XE_RTP_ACTION_FIELD_SET: Set a bit range
  * @reg_: Register
+ * @reg_type_: Register type - automatically expanded by MCR_REG/_MMIO
  * @mask_bits_: Mask of bits to be changed in the register, forming a field
  * @val_: Value to set in the field denoted by @mask_bits_
  * @...: Additional fields to override in the struct xe_rtp_action entry
@@ -256,28 +263,31 @@ struct xe_reg_sr;
  *
  *     REGNAME[<end>:<start>] = VALUE
  */
-#define XE_RTP_FIELD_SET(reg_, mask_bits_, val_, ...)                          \
-       .action = { .reg = reg_, .clr_bits = (mask_bits_), .set_bits = (val_),\
-                   .read_mask = (mask_bits_), ##__VA_ARGS__ }
+#define XE_RTP_ACTION_FIELD_SET(reg_, reg_type_, mask_bits_, val_, ...)                \
+       { .reg = (reg_), .reg_type = (reg_type_),                               \
+         .clr_bits = (mask_bits_), .set_bits = (val_),                         \
+         .read_mask = (mask_bits_), ##__VA_ARGS__ }
 
-#define XE_RTP_FIELD_SET_NO_READ_MASK(reg_, mask_bits_, val_, ...)             \
-       .action = { .reg = reg_, .clr_bits = (mask_bits_), .set_bits = (val_),\
-                   .read_mask = 0, ##__VA_ARGS__ }
+#define XE_RTP_ACTION_FIELD_SET_NO_READ_MASK(reg_, reg_type_, mask_bits_, val_, ...)   \
+       { .reg = (reg_), .reg_type = (reg_type_),                               \
+         .clr_bits = (mask_bits_), .set_bits = (val_),                         \
+         .read_mask = 0, ##__VA_ARGS__ }
 
 /**
- * XE_WHITELIST_REGISTER - Add register to userspace whitelist
+ * XE_RTP_ACTION_WHITELIST - Add register to userspace whitelist
  * @reg_: Register
- * @flags_: Whitelist-specific flags to set
+ * @reg_type_: Register type - automatically expanded by MCR_REG/_MMIO
+ * @val_: Whitelist-specific flags to set
  * @...: Additional fields to override in the struct xe_rtp_action entry
  *
  * Add a register to the whitelist, allowing userspace to modify the ster with
  * regular user privileges.
  */
-#define XE_WHITELIST_REGISTER(reg_, flags_, ...)                               \
+#define XE_RTP_ACTION_WHITELIST(reg_, reg_type_, val_, ...)                    \
        /* TODO fail build if ((flags) & ~(RING_FORCE_TO_NONPRIV_MASK_VALID)) */\
-       .action = { .reg = reg_, .set_bits = (flags_),                  \
-                   .clr_bits = RING_FORCE_TO_NONPRIV_MASK_VALID,               \
-                   ##__VA_ARGS__ }
+       { .reg = (reg_), .reg_type = (reg_type_), .set_bits = (val_),           \
+         .clr_bits = RING_FORCE_TO_NONPRIV_MASK_VALID,                         \
+         ##__VA_ARGS__ }
 
 /**
  * XE_RTP_NAME - Helper to set the name in xe_rtp_entry
@@ -324,7 +334,7 @@ struct xe_reg_sr;
  *             ...
  *             { XE_RTP_NAME("test-entry"),
  *               ...
- *               XE_RTP_SET(..., XE_RTP_ACTION_FLAG(FOREACH_ENGINE)),
+ *               XE_RTP_ACTION_SET(..., XE_RTP_ACTION_FLAG(FOREACH_ENGINE)),
  *               ...
  *             },
  *             ...
@@ -359,6 +369,33 @@ struct xe_reg_sr;
                CALL_FOR_EACH(__ADD_XE_RTP_RULE_PREFIX, r1, ##__VA_ARGS__)      \
        }
 
+/**
+ * XE_RTP_ACTIONS - Helper to set multiple actions to a struct xe_rtp_entry
+ * @a1: Action to take. Last part of XE_RTP_ACTION_*
+ * @...: Additional rules, defined like @r1
+ *
+ * At least one rule is needed and up to 4 are supported. Multiple rules are
+ * AND'ed together, i.e. all the rules must evaluate to true for the entry to
+ * be processed. See XE_RTP_MATCH_* for the possible match rules. Example:
+ *
+ * .. code-block:: c
+ *
+ *     const struct xe_rtp_entry wa_entries[] = {
+ *             ...
+ *             { XE_RTP_NAME("test-entry"),
+ *               XE_RTP_RULES(...),
+ *               XE_RTP_ACTIONS(SET(..), SET(...), CLR(...)),
+ *               ...
+ *             },
+ *             ...
+ *     };
+ */
+#define XE_RTP_ACTIONS(a1, ...)                                                        \
+       .n_actions = COUNT_ARGS(a1, ##__VA_ARGS__),                             \
+       .actions = (struct xe_rtp_action[]) {                                   \
+               CALL_FOR_EACH(__ADD_XE_RTP_ACTION_PREFIX, a1, ##__VA_ARGS__)    \
+       }
+
 void xe_rtp_process(const struct xe_rtp_entry *entries, struct xe_reg_sr *sr,
                    struct xe_gt *gt, struct xe_hw_engine *hwe);
 

diff --git a/drivers/gpu/drm/xe/xe_rtp_types.h b/drivers/gpu/drm/xe/xe_rtp_types.h
index f7efb17d00e5965c474c9b873d617b0f2d6f8a63..fac0bd6d5b1e01f328a788301c36cd42b89da210 100644 (file)
--- a/drivers/gpu/drm/xe/xe_rtp_types.h
+++ b/drivers/gpu/drm/xe/xe_rtp_types.h
@@ -95,9 +95,10 @@ struct xe_rtp_rule {
 /** struct xe_rtp_entry - Entry in an rtp table */
 struct xe_rtp_entry {
        const char *name;
-       const struct xe_rtp_action action;
+       const struct xe_rtp_action *actions;
        const struct xe_rtp_rule *rules;
        u8 n_rules;
+       u8 n_actions;
 #define XE_RTP_ENTRY_FLAG_FOREACH_ENGINE       BIT(0)
        u8 flags;
 };

diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
index 96b16b8d03cf01684f47e691bb5d5c8e5ea715df..3cc32e3e7a90fd9673c28ac601830819dfe1dace 100644 (file)
--- a/drivers/gpu/drm/xe/xe_tuning.c
+++ b/drivers/gpu/drm/xe/xe_tuning.c
@@ -19,7 +19,7 @@
 static const struct xe_rtp_entry gt_tunings[] = {
        { XE_RTP_NAME("Tuning: 32B Access Enable"),
          XE_RTP_RULES(PLATFORM(DG2)),
-         XE_RTP_SET(XEHP_SQCM, EN_32B_ACCESS)
+         XE_RTP_ACTIONS(SET(XEHP_SQCM, EN_32B_ACCESS))
        },
        {}
 };
@@ -27,8 +27,9 @@ static const struct xe_rtp_entry gt_tunings[] = {
 static const struct xe_rtp_entry context_tunings[] = {
        { XE_RTP_NAME("1604555607"),
          XE_RTP_RULES(GRAPHICS_VERSION(1200)),
-         XE_RTP_FIELD_SET_NO_READ_MASK(XEHP_FF_MODE2, FF_MODE2_TDS_TIMER_MASK,
-                                       FF_MODE2_TDS_TIMER_128)
+         XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(XEHP_FF_MODE2,
+                                               FF_MODE2_TDS_TIMER_MASK,
+                                               FF_MODE2_TDS_TIMER_128))
        },
        {}
 };

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index c1c098994c843f9e7a829d1c75d455445908d750..9d2e4555091c72575b7fbddbc63515ee3cfc1512 100644 (file)
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -103,86 +103,83 @@ static const struct xe_rtp_entry gt_was[] = {
          XE_RTP_RULES(MEDIA_VERSION_RANGE(1200, 1255),
                       ENGINE_CLASS(VIDEO_DECODE),
                       FUNC(match_14011060649)),
-         XE_RTP_SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS),
+         XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
          XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
        },
        { XE_RTP_NAME("16010515920"),
          XE_RTP_RULES(SUBPLATFORM(DG2, G10),
                       STEP(A0, B0),
                       ENGINE_CLASS(VIDEO_DECODE)),
-         XE_RTP_SET(VDBOX_CGCTL3F18(0), ALNUNIT_CLKGATE_DIS),
+         XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F18(0), ALNUNIT_CLKGATE_DIS)),
          XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
        },
        { XE_RTP_NAME("22010523718"),
          XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
-         XE_RTP_SET(UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS)
+         XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS))
        },
        { XE_RTP_NAME("14011006942"),
          XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
-         XE_RTP_SET(GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS)
+         XE_RTP_ACTIONS(SET(GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS))
        },
        { XE_RTP_NAME("14010948348"),
          XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0)),
-         XE_RTP_SET(UNSLCGCTL9430, MSQDUNIT_CLKGATE_DIS)
+         XE_RTP_ACTIONS(SET(UNSLCGCTL9430, MSQDUNIT_CLKGATE_DIS))
        },
        { XE_RTP_NAME("14011037102"),
          XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0)),
-         XE_RTP_SET(UNSLCGCTL9444, LTCDD_CLKGATE_DIS)
+         XE_RTP_ACTIONS(SET(UNSLCGCTL9444, LTCDD_CLKGATE_DIS))
        },
        { XE_RTP_NAME("14011371254"),
          XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0)),
-         XE_RTP_SET(GEN11_SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS)
+         XE_RTP_ACTIONS(SET(GEN11_SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS))
        },
-       { XE_RTP_NAME("14011431319/0"),
+       { XE_RTP_NAME("14011431319"),
          XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0)),
-         XE_RTP_SET(UNSLCGCTL9440,
-                    GAMTLBOACS_CLKGATE_DIS |
-                    GAMTLBVDBOX7_CLKGATE_DIS | GAMTLBVDBOX6_CLKGATE_DIS |
-                    GAMTLBVDBOX5_CLKGATE_DIS | GAMTLBVDBOX4_CLKGATE_DIS |
-                    GAMTLBVDBOX3_CLKGATE_DIS | GAMTLBVDBOX2_CLKGATE_DIS |
-                    GAMTLBVDBOX1_CLKGATE_DIS | GAMTLBVDBOX0_CLKGATE_DIS |
-                    GAMTLBKCR_CLKGATE_DIS | GAMTLBGUC_CLKGATE_DIS |
-                    GAMTLBBLT_CLKGATE_DIS)
-       },
-       { XE_RTP_NAME("14011431319/1"),
-         XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0)),
-         XE_RTP_SET(UNSLCGCTL9444,
-                    GAMTLBGFXA0_CLKGATE_DIS | GAMTLBGFXA1_CLKGATE_DIS |
-                    GAMTLBCOMPA0_CLKGATE_DIS | GAMTLBCOMPA1_CLKGATE_DIS |
-                    GAMTLBCOMPB0_CLKGATE_DIS | GAMTLBCOMPB1_CLKGATE_DIS |
-                    GAMTLBCOMPC0_CLKGATE_DIS | GAMTLBCOMPC1_CLKGATE_DIS |
-                    GAMTLBCOMPD0_CLKGATE_DIS | GAMTLBCOMPD1_CLKGATE_DIS |
-                    GAMTLBMERT_CLKGATE_DIS |
-                    GAMTLBVEBOX3_CLKGATE_DIS | GAMTLBVEBOX2_CLKGATE_DIS |
-                    GAMTLBVEBOX1_CLKGATE_DIS | GAMTLBVEBOX0_CLKGATE_DIS)
+         XE_RTP_ACTIONS(SET(UNSLCGCTL9440,
+                            GAMTLBOACS_CLKGATE_DIS |
+                            GAMTLBVDBOX7_CLKGATE_DIS | GAMTLBVDBOX6_CLKGATE_DIS |
+                            GAMTLBVDBOX5_CLKGATE_DIS | GAMTLBVDBOX4_CLKGATE_DIS |
+                            GAMTLBVDBOX3_CLKGATE_DIS | GAMTLBVDBOX2_CLKGATE_DIS |
+                            GAMTLBVDBOX1_CLKGATE_DIS | GAMTLBVDBOX0_CLKGATE_DIS |
+                            GAMTLBKCR_CLKGATE_DIS | GAMTLBGUC_CLKGATE_DIS |
+                            GAMTLBBLT_CLKGATE_DIS),
+                        SET(UNSLCGCTL9444,
+                            GAMTLBGFXA0_CLKGATE_DIS | GAMTLBGFXA1_CLKGATE_DIS |
+                            GAMTLBCOMPA0_CLKGATE_DIS | GAMTLBCOMPA1_CLKGATE_DIS |
+                            GAMTLBCOMPB0_CLKGATE_DIS | GAMTLBCOMPB1_CLKGATE_DIS |
+                            GAMTLBCOMPC0_CLKGATE_DIS | GAMTLBCOMPC1_CLKGATE_DIS |
+                            GAMTLBCOMPD0_CLKGATE_DIS | GAMTLBCOMPD1_CLKGATE_DIS |
+                            GAMTLBMERT_CLKGATE_DIS |
+                            GAMTLBVEBOX3_CLKGATE_DIS | GAMTLBVEBOX2_CLKGATE_DIS |
+                            GAMTLBVEBOX1_CLKGATE_DIS | GAMTLBVEBOX0_CLKGATE_DIS))
        },
        { XE_RTP_NAME("14010569222"),
          XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0)),
-         XE_RTP_SET(UNSLICE_UNIT_LEVEL_CLKGATE, GAMEDIA_CLKGATE_DIS)
+         XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, GAMEDIA_CLKGATE_DIS))
        },
        { XE_RTP_NAME("14011028019"),
          XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0)),
-         XE_RTP_SET(SSMCGCTL9530, RTFUNIT_CLKGATE_DIS)
+         XE_RTP_ACTIONS(SET(SSMCGCTL9530, RTFUNIT_CLKGATE_DIS))
        },
        { XE_RTP_NAME("14014830051"),
          XE_RTP_RULES(PLATFORM(DG2)),
-         XE_RTP_CLR(SARB_CHICKEN1, COMP_CKN_IN)
+         XE_RTP_ACTIONS(CLR(SARB_CHICKEN1, COMP_CKN_IN))
        },
        { XE_RTP_NAME("14015795083"),
          XE_RTP_RULES(PLATFORM(DG2)),
-         XE_RTP_CLR(GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE)
+         XE_RTP_ACTIONS(CLR(GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE))
        },
        { XE_RTP_NAME("14011059788"),
          XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
-         XE_RTP_SET(GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE)
+         XE_RTP_ACTIONS(SET(GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE))
        },
        { XE_RTP_NAME("1409420604"),
          XE_RTP_RULES(PLATFORM(DG1)),
-         XE_RTP_SET(SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS)
+         XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS))
        },
        { XE_RTP_NAME("1408615072"),
          XE_RTP_RULES(PLATFORM(DG1)),
-         XE_RTP_SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE_DIS_TGL)
+         XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE_DIS_TGL))
        },
        {}
 };
@@ -190,62 +187,67 @@ static const struct xe_rtp_entry gt_was[] = {
 static const struct xe_rtp_entry engine_was[] = {
        { XE_RTP_NAME("14015227452"),
          XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
-         XE_RTP_SET(GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE,
-                    XE_RTP_ACTION_FLAG(MASKED_REG))
+         XE_RTP_ACTIONS(SET(GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE,
+                            XE_RTP_ACTION_FLAG(MASKED_REG)))
        },
        { XE_RTP_NAME("1606931601"),
          XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
-         XE_RTP_SET(GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ,
-                    XE_RTP_ACTION_FLAG(MASKED_REG))
+         XE_RTP_ACTIONS(SET(GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ,
+                            XE_RTP_ACTION_FLAG(MASKED_REG)))
        },
        { XE_RTP_NAME("22010931296, 18011464164, 14010919138"),
          XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)),
-         XE_RTP_SET(GEN7_FF_THREAD_MODE, GEN12_FF_TESSELATION_DOP_GATE_DISABLE)
+         XE_RTP_ACTIONS(SET(GEN7_FF_THREAD_MODE,
+                            GEN12_FF_TESSELATION_DOP_GATE_DISABLE))
        },
        { XE_RTP_NAME("14010826681, 1606700617, 22010271021"),
          XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
-         XE_RTP_SET(GEN9_CS_DEBUG_MODE1, FF_DOP_CLOCK_GATE_DISABLE,
-                    XE_RTP_ACTION_FLAG(MASKED_REG))
+         XE_RTP_ACTIONS(SET(GEN9_CS_DEBUG_MODE1, FF_DOP_CLOCK_GATE_DISABLE,
+                            XE_RTP_ACTION_FLAG(MASKED_REG)))
        },
        { XE_RTP_NAME("18019627453"),
          XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
-         XE_RTP_SET(GEN9_CS_DEBUG_MODE1, FF_DOP_CLOCK_GATE_DISABLE,
-                    XE_RTP_ACTION_FLAG(MASKED_REG))
+         XE_RTP_ACTIONS(SET(GEN9_CS_DEBUG_MODE1, FF_DOP_CLOCK_GATE_DISABLE,
+                            XE_RTP_ACTION_FLAG(MASKED_REG)))
        },
        { XE_RTP_NAME("1409804808"),
          XE_RTP_RULES(GRAPHICS_VERSION(1200),
                       ENGINE_CLASS(RENDER),
                       IS_INTEGRATED),
-         XE_RTP_SET(GEN7_ROW_CHICKEN2, GEN12_PUSH_CONST_DEREF_HOLD_DIS,
-                    XE_RTP_ACTION_FLAG(MASKED_REG))
+         XE_RTP_ACTIONS(SET(GEN7_ROW_CHICKEN2, GEN12_PUSH_CONST_DEREF_HOLD_DIS,
+                            XE_RTP_ACTION_FLAG(MASKED_REG)))
        },
        { XE_RTP_NAME("14010229206, 1409085225"),
          XE_RTP_RULES(GRAPHICS_VERSION(1200),
                       ENGINE_CLASS(RENDER),
                       IS_INTEGRATED),
-         XE_RTP_SET(GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH,
-                    XE_RTP_ACTION_FLAG(MASKED_REG))
+         XE_RTP_ACTIONS(SET(GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH,
+                            XE_RTP_ACTION_FLAG(MASKED_REG)))
        },
        { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
          XE_RTP_RULES(PLATFORM(TIGERLAKE), ENGINE_CLASS(RENDER)),
-         XE_RTP_SET(RING_PSMI_CTL(RENDER_RING_BASE),
-                    GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
-                    GEN8_RC_SEMA_IDLE_MSG_DISABLE, XE_RTP_ACTION_FLAG(MASKED_REG))
+         XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
+                            GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
+                            GEN8_RC_SEMA_IDLE_MSG_DISABLE,
+                            XE_RTP_ACTION_FLAG(MASKED_REG)))
        },
        { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
          XE_RTP_RULES(PLATFORM(ROCKETLAKE), ENGINE_CLASS(RENDER)),
-         XE_RTP_SET(RING_PSMI_CTL(RENDER_RING_BASE),
-                    GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
-                    GEN8_RC_SEMA_IDLE_MSG_DISABLE, XE_RTP_ACTION_FLAG(MASKED_REG))
+         XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
+                            GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
+                            GEN8_RC_SEMA_IDLE_MSG_DISABLE,
+                            XE_RTP_ACTION_FLAG(MASKED_REG)))
        },
        { XE_RTP_NAME("1406941453"),
          XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
-         XE_RTP_SET(GEN10_SAMPLER_MODE, ENABLE_SMALLPL, XE_RTP_ACTION_FLAG(MASKED_REG))
+         XE_RTP_ACTIONS(SET(GEN10_SAMPLER_MODE, ENABLE_SMALLPL,
+                            XE_RTP_ACTION_FLAG(MASKED_REG)))
        },
        { XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"),
          XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)),
-         XE_RTP_SET(GEN7_FF_SLICE_CS_CHICKEN1, GEN9_FFSC_PERCTX_PREEMPT_CTRL,
-                    XE_RTP_ACTION_FLAG(MASKED_REG))
+         XE_RTP_ACTIONS(SET(GEN7_FF_SLICE_CS_CHICKEN1,
+                            GEN9_FFSC_PERCTX_PREEMPT_CTRL,
+                            XE_RTP_ACTION_FLAG(MASKED_REG)))
        },
        {}
 };
@@ -253,33 +255,35 @@ static const struct xe_rtp_entry engine_was[] = {
 static const struct xe_rtp_entry lrc_was[] = {
        { XE_RTP_NAME("1409342910, 14010698770, 14010443199, 1408979724, 1409178076, 1409207793, 1409217633, 1409252684, 1409347922, 1409142259"),
          XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
-         XE_RTP_SET(GEN11_COMMON_SLICE_CHICKEN3,
-                    GEN12_DISABLE_CPS_AWARE_COLOR_PIPE,
-                    XE_RTP_ACTION_FLAG(MASKED_REG))
+         XE_RTP_ACTIONS(SET(GEN11_COMMON_SLICE_CHICKEN3,
+                            GEN12_DISABLE_CPS_AWARE_COLOR_PIPE,
+                            XE_RTP_ACTION_FLAG(MASKED_REG)))
        },
        { XE_RTP_NAME("WaDisableGPGPUMidThreadPreemption"),
          XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
-         XE_RTP_FIELD_SET(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
-                          GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL,
-                          XE_RTP_ACTION_FLAG(MASKED_REG))
+         XE_RTP_ACTIONS(FIELD_SET(GEN8_CS_CHICKEN1,
+                                  GEN9_PREEMPT_GPGPU_LEVEL_MASK,
+                                  GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL,
+                                  XE_RTP_ACTION_FLAG(MASKED_REG)))
        },
        { XE_RTP_NAME("16011163337"),
          XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
          /* read verification is ignored due to 1608008084. */
-         XE_RTP_FIELD_SET_NO_READ_MASK(GEN12_FF_MODE2, FF_MODE2_GS_TIMER_MASK,
-                                       FF_MODE2_GS_TIMER_224)
+         XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(GEN12_FF_MODE2,
+                                               FF_MODE2_GS_TIMER_MASK,
+                                               FF_MODE2_GS_TIMER_224))
        },
        { XE_RTP_NAME("1409044764"),
          XE_RTP_RULES(PLATFORM(DG1)),
-         XE_RTP_CLR(GEN11_COMMON_SLICE_CHICKEN3,
-                    DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN,
-                    XE_RTP_ACTION_FLAG(MASKED_REG))
+         XE_RTP_ACTIONS(CLR(GEN11_COMMON_SLICE_CHICKEN3,
+                            DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN,
+                            XE_RTP_ACTION_FLAG(MASKED_REG)))
        },
        { XE_RTP_NAME("22010493298"),
          XE_RTP_RULES(PLATFORM(DG1)),
-         XE_RTP_SET(HIZ_CHICKEN,
-                    DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE,
-                    XE_RTP_ACTION_FLAG(MASKED_REG))
+         XE_RTP_ACTIONS(SET(HIZ_CHICKEN,
+                            DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE,
+                            XE_RTP_ACTION_FLAG(MASKED_REG)))
        },
        {}
 };