arm64: dts: imx8mp-phyboard-pollux-rdk: Change debug UART

With the first redesign the debug UART had changed from
UART2 to UART1.
As the first hardware revision is considered as alpha and
will not be supported in future. The old setup will not
be preserved.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
index f33f2c0a22a2b43bdcd54dc14007b3bd34802dda..e5d5e6067145a213a4e6cc76926734f5c281849a 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
@@ -16,7 +16,7 @@
                     "phytec,imx8mp-phycore-som", "fsl,imx8mp";
 
        chosen {
-               stdout-path = &uart2;
+               stdout-path = &uart1;
        };
 
        reg_usdhc2_vmmc: regulator-usdhc2 {
@@ -95,9 +95,9 @@
 };
 
 /* debug console */
-&uart2 {
+&uart1 {
        pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_uart2>;
+       pinctrl-0 = <&pinctrl_uart1>;
        status = "okay";
 };
 
@@ -154,10 +154,10 @@
                >;
        };
 
-       pinctrl_uart2: uart2grp {
+       pinctrl_uart1: uart1grp {
                fsl,pins = <
-                       MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX    0x49
-                       MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX    0x49
+                       MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX    0x49
+                       MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX    0x49
                >;
        };