drm/i915/tgl: Implement WA_16011163337

Set GS Timer to 224. Combine with Wa_1604555607 due to register FF_MODE2
not being able to be read.

V2: Math issue fixed

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Caz Yokoyama <caz.yokoyama@intel.com>
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20200603221150.14745-1-clinton.a.taylor@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 30cd798b96642abacdf991e61c458682dfd8c3b8..3eec31c5a714e60b94269106c42ce8e4e549fb93 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -609,11 +609,14 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
         * Wa_1604555607:gen12 and Wa_1608008084:gen12
         * FF_MODE2 register will return the wrong value when read. The default
         * value for this register is zero for all fields and there are no bit
-        * masks. So instead of doing a RMW we should just write the TDS timer
-        * value for Wa_1604555607.
+        * masks. So instead of doing a RMW we should just write the GS Timer
+        * and TDS timer values for Wa_1604555607 and Wa_16011163337.
         */
-       wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK,
-              FF_MODE2_TDS_TIMER_128, 0);
+       wa_add(wal,
+              FF_MODE2,
+              FF_MODE2_GS_TIMER_MASK | FF_MODE2_TDS_TIMER_MASK,
+              FF_MODE2_GS_TIMER_224  | FF_MODE2_TDS_TIMER_128,
+              0);
 
        /* WaDisableGPGPUMidThreadPreemption:tgl */
        WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 578cfe11cbb9795683a119e61d960a0d276f0944..96d351fbeebb07cc4bf8e748998e10435b5b5d54 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8004,6 +8004,8 @@ enum {
 #define   PER_PIXEL_ALPHA_BYPASS_EN            (1 << 7)
 
 #define FF_MODE2                       _MMIO(0x6604)
+#define   FF_MODE2_GS_TIMER_MASK       REG_GENMASK(31, 24)
+#define   FF_MODE2_GS_TIMER_224                REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
 #define   FF_MODE2_TDS_TIMER_MASK      REG_GENMASK(23, 16)
 #define   FF_MODE2_TDS_TIMER_128       REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)