drm: rcar-du: lvds: Fix LVDS startup on R-Car Gen2
authorSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Fri, 12 Jan 2018 20:12:05 +0000 (23:12 +0300)
committerLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Wed, 14 Feb 2018 17:54:41 +0000 (19:54 +0200)
According to the latest revision 2.00 of the R-Car Gen2 manual, the LVDS
and the bias circuit must be enabled after the LVDS I/O pins are
enabled, not before. Fix the Gen2 LVDS startup sequence accordingly.

While at it, also fix the comment preceding the first LVDCR0 write that
still talks about hardcoding the LVDS mode 0.

Fixes: 90374b5c25c9 ("drm/rcar-du: Add internal LVDS encoder support")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c

index abbb7b25129a925725b88d0007ce6ed92d452559..dcffd3b59b6943c7d98990731afbdd5976c32fe2 100644 (file)
@@ -59,11 +59,8 @@ static void rcar_du_lvdsenc_start_gen2(struct rcar_du_lvdsenc *lvds,
 
        rcar_lvds_write(lvds, LVDPLLCR, pllcr);
 
-       /*
-        * Select the input, hardcode mode 0, enable LVDS operation and turn
-        * bias circuitry on.
-        */
-       lvdcr0 = (lvds->mode << LVDCR0_LVMD_SHIFT) | LVDCR0_BEN | LVDCR0_LVEN;
+       /* Select the input and set the LVDS mode. */
+       lvdcr0 = lvds->mode << LVDCR0_LVMD_SHIFT;
        if (rcrtc->index == 2)
                lvdcr0 |= LVDCR0_DUSEL;
        rcar_lvds_write(lvds, LVDCR0, lvdcr0);
@@ -73,6 +70,10 @@ static void rcar_du_lvdsenc_start_gen2(struct rcar_du_lvdsenc *lvds,
                        LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) |
                        LVDCR1_CHSTBY(1) | LVDCR1_CHSTBY(0) | LVDCR1_CLKSTBY);
 
+       /* Enable LVDS operation and turn bias circuitry on. */
+       lvdcr0 |= LVDCR0_BEN | LVDCR0_LVEN;
+       rcar_lvds_write(lvds, LVDCR0, lvdcr0);
+
        /*
         * Turn the PLL on, wait for the startup delay, and turn the output
         * on.