drm/amdgpu: Switch to LFB for USBC PD FW in psp v13

Add USBC PD FW implementation here to be used with relevant ASICs.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Alexander Deucher <Alexander.Deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
index c8949add88f3831bfcc6f9cc053e19312ce0652c..e1046bb3bab00033773066cc4ec7a3c5d65505f0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
@@ -35,6 +35,12 @@ MODULE_FIRMWARE("amdgpu/yellow_carp_asd.bin");
 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin");
 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin");
 
+/* For large FW files the time to complete can be very long */
+#define USBC_PD_POLLING_LIMIT_S 240
+
+/* Read USB-PD from LFB */
+#define GFX_CMD_USB_PD_USE_LFB 0x480
+
 static int psp_v13_0_init_microcode(struct psp_context *psp)
 {
        struct amdgpu_device *adev = psp->adev;
@@ -382,6 +388,64 @@ static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
                WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
 }
 
+static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)
+{
+       struct amdgpu_device *adev = psp->adev;
+       uint32_t reg_status;
+       int ret, i = 0;
+
+       /*
+        * LFB address which is aligned to 1MB address and has to be
+        * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P
+        * register
+        */
+       WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
+
+       ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
+                            0x80000000, 0x80000000, false);
+       if (ret)
+               return ret;
+
+       /* Fireup interrupt so PSP can pick up the address */
+       WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16));
+
+       /* FW load takes very long time */
+       do {
+               msleep(1000);
+               reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35);
+
+               if (reg_status & 0x80000000)
+                       goto done;
+
+       } while (++i < USBC_PD_POLLING_LIMIT_S);
+
+       return -ETIME;
+done:
+
+       if ((reg_status & 0xFFFF) != 0) {
+               DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n",
+                               reg_status & 0xFFFF);
+               return -EIO;
+       }
+
+       return 0;
+}
+
+static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
+{
+       struct amdgpu_device *adev = psp->adev;
+       int ret;
+
+       WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
+
+       ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
+                                    0x80000000, 0x80000000, false);
+       if (!ret)
+               *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36);
+
+       return ret;
+}
+
 static const struct psp_funcs psp_v13_0_funcs = {
        .init_microcode = psp_v13_0_init_microcode,
        .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb,
@@ -393,6 +457,8 @@ static const struct psp_funcs psp_v13_0_funcs = {
        .ring_destroy = psp_v13_0_ring_destroy,
        .ring_get_wptr = psp_v13_0_ring_get_wptr,
        .ring_set_wptr = psp_v13_0_ring_set_wptr,
+       .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw,
+       .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw
 };
 
 void psp_v13_0_set_psp_funcs(struct psp_context *psp)