amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, NULL, count);
                break;
        case ACA_ERROR_TYPE_DEFERRED:
+               amdgpu_ras_error_statistic_de_count(err_data, &mcm_info, NULL, count);
+               break;
        default:
                break;
        }
                smu_type = ACA_SMU_TYPE_UE;
                break;
        case ACA_ERROR_TYPE_CE:
+       case ACA_ERROR_TYPE_DEFERRED:
                smu_type = ACA_SMU_TYPE_CE;
                break;
        default:
 
        if (amdgpu_ras_query_error_status(obj->adev, &info))
                return -EINVAL;
 
-       return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
-                         "ce", info.ce_count);
+       return sysfs_emit(buf, "%s: %lu\n%s: %lu\n%s: %lu\n", "ue", info.ue_count,
+                         "ce", info.ce_count, "de", info.ue_count);
 }
 
 static int amdgpu_ras_query_error_status_helper(struct amdgpu_device *adev,
                        ret = amdgpu_aca_log_ras_error_data(adev, blk, ACA_ERROR_TYPE_CE, err_data);
                        if (ret)
                                return ret;
+
+                       ret = amdgpu_aca_log_ras_error_data(adev, blk, ACA_ERROR_TYPE_DEFERRED, err_data);
+                       if (ret)
+                               return ret;
                } else {
                        /* FIXME: add code to check return value later */
                        amdgpu_mca_smu_log_ras_error(adev, blk, AMDGPU_MCA_ERROR_TYPE_UE, err_data, qctx);