ARM: tegra: Add clock-cells property to PMC

Tegra PMC has clk_out_1, clk_out_2, clk_out_3, and blink clock.

These clocks were erroneously provided by the clock and reset controller
and are now provided by the PMC instead because that's where the primary
controls are.

This patch adds #clock-cells property with 1 clock specifier to the
Tegra PMC node in device tree.

Tested-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 0d7a6327e404a6eca0353de81eb2acd18b5b0e2b..450a1f1b12a008c0a1654307f887bc3f9781782a 100644 (file)
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -4,6 +4,7 @@
 #include <dt-bindings/memory/tegra114-mc.h>
 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/tegra-pmc.h>
 
 / {
        compatible = "nvidia,tegra114";
@@ -514,11 +515,12 @@
                status = "disabled";
        };
 
-       pmc@7000e400 {
+       tegra_pmc: pmc@7000e400 {
                compatible = "nvidia,tegra114-pmc";
                reg = <0x7000e400 0x400>;
                clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
                clock-names = "pclk", "clk32k_in";
+               #clock-cells = <1>;
        };
 
        fuse@7000f800 {

diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 7f330b1f150f8649056df2768cbf04ffed81c683..94cac13d3e50943807b765f89629bbac8f02cfc7 100644 (file)
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -6,6 +6,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/tegra124-car.h>
 #include <dt-bindings/thermal/tegra124-soctherm.h>
+#include <dt-bindings/soc/tegra-pmc.h>
 
 / {
        compatible = "nvidia,tegra124";
@@ -595,11 +596,12 @@
                clocks = <&tegra_car TEGRA124_CLK_RTC>;
        };
 
-       pmc@7000e400 {
+       tegra_pmc: pmc@7000e400 {
                compatible = "nvidia,tegra124-pmc";
                reg = <0x0 0x7000e400 0x0 0x400>;
                clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
                clock-names = "pclk", "clk32k_in";
+               #clock-cells = <1>;
        };
 
        fuse@7000f800 {

diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 9c58e7fcf5c04fd95a7df2a291962e0ceda3afa9..c3b8ad53b967620e78e9277121e7a6c35be9926a 100644 (file)
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -4,6 +4,7 @@
 #include <dt-bindings/memory/tegra20-mc.h>
 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/tegra-pmc.h>
 
 / {
        compatible = "nvidia,tegra20";
@@ -608,11 +609,12 @@
                status = "disabled";
        };
 
-       pmc@7000e400 {
+       tegra_pmc: pmc@7000e400 {
                compatible = "nvidia,tegra20-pmc";
                reg = <0x7000e400 0x400>;
                clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
                clock-names = "pclk", "clk32k_in";
+               #clock-cells = <1>;
        };
 
        mc: memory-controller@7000f000 {

diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 55ae050042cec3bc8d9c5efb674cd1fdf93f503a..d2d05f1da2745d5ce5fe35df7d60c88e0704a5d0 100644 (file)
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -4,6 +4,7 @@
 #include <dt-bindings/memory/tegra30-mc.h>
 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/tegra-pmc.h>
 
 / {
        compatible = "nvidia,tegra30";
@@ -714,11 +715,12 @@
                status = "disabled";
        };
 
-       pmc@7000e400 {
+       tegra_pmc: pmc@7000e400 {
                compatible = "nvidia,tegra30-pmc";
                reg = <0x7000e400 0x400>;
                clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
                clock-names = "pclk", "clk32k_in";
+               #clock-cells = <1>;
        };
 
        mc: memory-controller@7000f000 {