drm/amdgpu: add xcc index argument to rlc safe_mode func (v4)

v1: To support multple XCD case (Le)
v2: unify naming style (Le)
v3: apply the changes to gc v11_0 (Hawking)
v4: apply the changes to gc SOC21 (Morris)

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Morris Zhang <Shiwu.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c
index 85fb730d9fc84fba4dc41f6cade87172644ba938..d3bed9a3e61fa748c863b32efefe3d834d09bedf 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c
@@ -34,9 +34,9 @@
  *
  * Set RLC enter into safe mode if RLC is enabled and haven't in safe mode.
  */
-void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev)
+void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev, int xcc_id)
 {
-       if (adev->gfx.rlc.in_safe_mode)
+       if (adev->gfx.rlc.in_safe_mode[xcc_id])
                return;
 
        /* if RLC is not enabled, do nothing */
@@ -46,8 +46,8 @@ void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev)
        if (adev->cg_flags &
            (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
             AMD_CG_SUPPORT_GFX_3D_CGCG)) {
-               adev->gfx.rlc.funcs->set_safe_mode(adev);
-               adev->gfx.rlc.in_safe_mode = true;
+               adev->gfx.rlc.funcs->set_safe_mode(adev, xcc_id);
+               adev->gfx.rlc.in_safe_mode[xcc_id] = true;
        }
 }
 
@@ -58,9 +58,9 @@ void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev)
  *
  * Set RLC exit safe mode if RLC is enabled and have entered into safe mode.
  */
-void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev)
+void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev, int xcc_id)
 {
-       if (!(adev->gfx.rlc.in_safe_mode))
+       if (!(adev->gfx.rlc.in_safe_mode[xcc_id]))
                return;
 
        /* if RLC is not enabled, do nothing */
@@ -70,8 +70,8 @@ void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev)
        if (adev->cg_flags &
            (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
             AMD_CG_SUPPORT_GFX_3D_CGCG)) {
-               adev->gfx.rlc.funcs->unset_safe_mode(adev);
-               adev->gfx.rlc.in_safe_mode = false;
+               adev->gfx.rlc.funcs->unset_safe_mode(adev, xcc_id);
+               adev->gfx.rlc.in_safe_mode[xcc_id] = false;
        }
 }
 

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
index 23f060db9255ce92479f112f02d00b520f8a1a77..80b263646966eef671ce23ee600e079350ebee82 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
@@ -157,8 +157,8 @@ typedef struct _RLC_TABLE_OF_CONTENT {
 
 struct amdgpu_rlc_funcs {
        bool (*is_rlc_enabled)(struct amdgpu_device *adev);
-       void (*set_safe_mode)(struct amdgpu_device *adev);
-       void (*unset_safe_mode)(struct amdgpu_device *adev);
+       void (*set_safe_mode)(struct amdgpu_device *adev, int xcc_id);
+       void (*unset_safe_mode)(struct amdgpu_device *adev, int xcc_id);
        int  (*init)(struct amdgpu_device *adev);
        u32  (*get_csb_size)(struct amdgpu_device *adev);
        void (*get_csb_buffer)(struct amdgpu_device *adev, volatile u32 *buffer);
@@ -201,7 +201,7 @@ struct amdgpu_rlc {
        u32                     cp_table_size;
 
        /* safe mode for updating CG/PG state */
-       bool in_safe_mode;
+       bool in_safe_mode[8];
        const struct amdgpu_rlc_funcs *funcs;
 
        /* for firmware data */
@@ -260,8 +260,8 @@ struct amdgpu_rlc {
        struct amdgpu_rlcg_reg_access_ctrl reg_access_ctrl;
 };
 
-void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev);
-void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev);
+void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev, int xcc_id);
+void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev, int xcc_id);
 int amdgpu_gfx_rlc_init_sr(struct amdgpu_device *adev, u32 dws);
 int amdgpu_gfx_rlc_init_csb(struct amdgpu_device *adev);
 int amdgpu_gfx_rlc_init_cpt(struct amdgpu_device *adev);

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 323f5b8927ad114edc77beaee78e4a05f0fb44eb..8bd07ff59671889fe7587e7f955dffd6d9ce250c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -7571,7 +7571,7 @@ static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
        return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
 }
 
-static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
+static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
 {
        uint32_t data;
        unsigned i;
@@ -7612,7 +7612,7 @@ static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
        }
 }
 
-static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
+static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
 {
        uint32_t data;
 
@@ -7959,7 +7959,7 @@ static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_d
 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
                                            bool enable)
 {
-       amdgpu_gfx_rlc_enter_safe_mode(adev);
+       amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
 
        if (enable) {
                /* enable FGCG firstly*/
@@ -7998,7 +7998,7 @@ static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
             AMD_CG_SUPPORT_GFX_3D_CGLS))
                gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
 
-       amdgpu_gfx_rlc_exit_safe_mode(adev);
+       amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
 
        return 0;
 }
@@ -8092,11 +8092,11 @@ static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
 
 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
 {
-       amdgpu_gfx_rlc_enter_safe_mode(adev);
+       amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
 
        gfx_v10_cntl_power_gating(adev, enable);
 
-       amdgpu_gfx_rlc_exit_safe_mode(adev);
+       amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
 }
 
 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 50d0ff9ca25993b9a463fbe7fbf13856cdeb736e..d3c89e6c0c03518558becd2ec65cd6fe698ee38c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -123,8 +123,8 @@ static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
                                           uint16_t pasid, uint32_t flush_type,
                                           bool all_hub, uint8_t dst_sel);
-static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev);
-static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev);
+static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
+static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev,
                                      bool enable);
 
@@ -4532,7 +4532,7 @@ static int gfx_v11_0_soft_reset(void *handle)
        tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0);
        WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp);
 
-       gfx_v11_0_set_safe_mode(adev);
+       gfx_v11_0_set_safe_mode(adev, 0);
 
        for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
                for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
@@ -4632,7 +4632,7 @@ static int gfx_v11_0_soft_reset(void *handle)
        tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);
        WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp);
 
-       gfx_v11_0_unset_safe_mode(adev);
+       gfx_v11_0_unset_safe_mode(adev, 0);
 
        return gfx_v11_0_cp_resume(adev);
 }
@@ -4798,7 +4798,7 @@ static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev)
        return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
 }
 
-static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev)
+static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
 {
        uint32_t data;
        unsigned i;
@@ -4817,7 +4817,7 @@ static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev)
        }
 }
 
-static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev)
+static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
 {
        WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK);
 }
@@ -5045,7 +5045,7 @@ static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
 static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev,
                                            bool enable)
 {
-       amdgpu_gfx_rlc_enter_safe_mode(adev);
+       amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
 
        gfx_v11_0_update_coarse_grain_clock_gating(adev, enable);
 
@@ -5065,7 +5065,7 @@ static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev,
             AMD_CG_SUPPORT_GFX_3D_CGLS))
                gfx_v11_0_enable_gui_idle_interrupt(adev, enable);
 
-       amdgpu_gfx_rlc_exit_safe_mode(adev);
+       amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
 
        return 0;
 }
@@ -5133,11 +5133,11 @@ static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable)
 
 static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable)
 {
-       amdgpu_gfx_rlc_enter_safe_mode(adev);
+       amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
 
        gfx_v11_cntl_power_gating(adev, enable);
 
-       amdgpu_gfx_rlc_exit_safe_mode(adev);
+       amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
 }
 
 static int gfx_v11_0_set_powergating_state(void *handle,

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index d055e44eee1d80bc58cd514e8ce785711cf49496..d56dda5fc5883f2b0846e6dbf41eb4361b88ee97 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -3362,7 +3362,7 @@ static bool gfx_v7_0_is_rlc_enabled(struct amdgpu_device *adev)
        return true;
 }
 
-static void gfx_v7_0_set_safe_mode(struct amdgpu_device *adev)
+static void gfx_v7_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
 {
        u32 tmp, i, mask;
 
@@ -3384,7 +3384,7 @@ static void gfx_v7_0_set_safe_mode(struct amdgpu_device *adev)
        }
 }
 
-static void gfx_v7_0_unset_safe_mode(struct amdgpu_device *adev)
+static void gfx_v7_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
 {
        u32 tmp;
 

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index b604808761499dde387d20d4b05fb2d7c8275034..278416acf0608ac731d7d898fe3c85da0f9e650c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4903,7 +4903,7 @@ static int gfx_v8_0_hw_fini(void *handle)
                pr_debug("For SRIOV client, shouldn't do anything.\n");
                return 0;
        }
-       amdgpu_gfx_rlc_enter_safe_mode(adev);
+       amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
        if (!gfx_v8_0_wait_for_idle(adev))
                gfx_v8_0_cp_enable(adev, false);
        else
@@ -4912,7 +4912,7 @@ static int gfx_v8_0_hw_fini(void *handle)
                adev->gfx.rlc.funcs->stop(adev);
        else
                pr_err("rlc is busy, skip halt rlc\n");
-       amdgpu_gfx_rlc_exit_safe_mode(adev);
+       amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
 
        return 0;
 }
@@ -5377,7 +5377,7 @@ static int gfx_v8_0_set_powergating_state(void *handle,
                                AMD_PG_SUPPORT_RLC_SMU_HS |
                                AMD_PG_SUPPORT_CP |
                                AMD_PG_SUPPORT_GFX_DMG))
-               amdgpu_gfx_rlc_enter_safe_mode(adev);
+               amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
        switch (adev->asic_type) {
        case CHIP_CARRIZO:
        case CHIP_STONEY:
@@ -5431,7 +5431,7 @@ static int gfx_v8_0_set_powergating_state(void *handle,
                                AMD_PG_SUPPORT_RLC_SMU_HS |
                                AMD_PG_SUPPORT_CP |
                                AMD_PG_SUPPORT_GFX_DMG))
-               amdgpu_gfx_rlc_exit_safe_mode(adev);
+               amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
        return 0;
 }
 
@@ -5536,7 +5536,7 @@ static bool gfx_v8_0_is_rlc_enabled(struct amdgpu_device *adev)
        return true;
 }
 
-static void gfx_v8_0_set_safe_mode(struct amdgpu_device *adev)
+static void gfx_v8_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
 {
        uint32_t data;
        unsigned i;
@@ -5563,7 +5563,7 @@ static void gfx_v8_0_set_safe_mode(struct amdgpu_device *adev)
        }
 }
 
-static void gfx_v8_0_unset_safe_mode(struct amdgpu_device *adev)
+static void gfx_v8_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
 {
        uint32_t data;
        unsigned i;
@@ -5622,7 +5622,7 @@ static void gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
 {
        uint32_t temp, data;
 
-       amdgpu_gfx_rlc_enter_safe_mode(adev);
+       amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
 
        /* It is disabled by HW by default */
        if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
@@ -5718,7 +5718,7 @@ static void gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
                gfx_v8_0_wait_for_rlc_serdes(adev);
        }
 
-       amdgpu_gfx_rlc_exit_safe_mode(adev);
+       amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
 }
 
 static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
@@ -5728,7 +5728,7 @@ static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
 
        temp = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
 
-       amdgpu_gfx_rlc_enter_safe_mode(adev);
+       amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
 
        if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
                temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
@@ -5811,7 +5811,7 @@ static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
 
        gfx_v8_0_wait_for_rlc_serdes(adev);
 
-       amdgpu_gfx_rlc_exit_safe_mode(adev);
+       amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
 }
 static int gfx_v8_0_update_gfx_clock_gating(struct amdgpu_device *adev,
                                            bool enable)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 2fa7adef18a9100cd589fefe3835efa1b521d595..bce6919d666ad0655299a359bd8f2db560186318 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4623,7 +4623,7 @@ static bool gfx_v9_0_is_rlc_enabled(struct amdgpu_device *adev)
        return true;
 }
 
-static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev)
+static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
 {
        uint32_t data;
        unsigned i;
@@ -4640,7 +4640,7 @@ static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev)
        }
 }
 
-static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev)
+static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
 {
        uint32_t data;
 
@@ -4651,7 +4651,7 @@ static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev)
 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
                                                bool enable)
 {
-       amdgpu_gfx_rlc_enter_safe_mode(adev);
+       amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
 
        if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
                gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
@@ -4663,7 +4663,7 @@ static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
                        gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
        }
 
-       amdgpu_gfx_rlc_exit_safe_mode(adev);
+       amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
 }
 
 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
@@ -4690,7 +4690,7 @@ static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
 {
        uint32_t data, def;
 
-       amdgpu_gfx_rlc_enter_safe_mode(adev);
+       amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
 
        /* It is disabled by HW by default */
        if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
@@ -4757,7 +4757,7 @@ static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
                }
        }
 
-       amdgpu_gfx_rlc_exit_safe_mode(adev);
+       amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
 }
 
 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
@@ -4768,7 +4768,7 @@ static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
        if (!adev->gfx.num_gfx_rings)
                return;
 
-       amdgpu_gfx_rlc_enter_safe_mode(adev);
+       amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
 
        /* Enable 3D CGCG/CGLS */
        if (enable) {
@@ -4812,7 +4812,7 @@ static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
                        WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
        }
 
-       amdgpu_gfx_rlc_exit_safe_mode(adev);
+       amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
 }
 
 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
@@ -4820,7 +4820,7 @@ static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
 {
        uint32_t def, data;
 
-       amdgpu_gfx_rlc_enter_safe_mode(adev);
+       amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
 
        if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
                def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
@@ -4864,7 +4864,7 @@ static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
                        WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
        }
 
-       amdgpu_gfx_rlc_exit_safe_mode(adev);
+       amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
 }
 
 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index b67be666f38a1b52d1b08d7a995c3a4995c4c78f..baa10ee8ec697567fc61a3ca63c1407099aa2148 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -1090,14 +1090,14 @@ static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev)
        return true;
 }
 
-static void gfx_v9_4_3_set_safe_mode(struct amdgpu_device *adev)
+static void gfx_v9_4_3_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
 {
        uint32_t data;
        unsigned i;
 
        data = RLC_SAFE_MODE__CMD_MASK;
        data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
-       WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data);
+       WREG32_SOC15(GC, xcc_id, regRLC_SAFE_MODE, data);
 
        /* wait for RLC_SAFE_MODE */
        for (i = 0; i < adev->usec_timeout; i++) {
@@ -1107,12 +1107,12 @@ static void gfx_v9_4_3_set_safe_mode(struct amdgpu_device *adev)
        }
 }
 
-static void gfx_v9_4_3_unset_safe_mode(struct amdgpu_device *adev)
+static void gfx_v9_4_3_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
 {
        uint32_t data;
 
        data = RLC_SAFE_MODE__CMD_MASK;
-       WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data);
+       WREG32_SOC15(GC, xcc_id, regRLC_SAFE_MODE, data);
 }
 
 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev)
@@ -2125,7 +2125,7 @@ static void gfx_v9_4_3_update_medium_grain_clock_gating(struct amdgpu_device *ad
 {
        uint32_t data, def;
 
-       amdgpu_gfx_rlc_enter_safe_mode(adev);
+       amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id);
 
        /* It is disabled by HW by default */
        if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
@@ -2186,7 +2186,7 @@ static void gfx_v9_4_3_update_medium_grain_clock_gating(struct amdgpu_device *ad
                }
        }
 
-       amdgpu_gfx_rlc_exit_safe_mode(adev);
+       amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id);
 }
 
 static void gfx_v9_4_3_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
@@ -2194,7 +2194,7 @@ static void gfx_v9_4_3_update_coarse_grain_clock_gating(struct amdgpu_device *ad
 {
        uint32_t def, data;
 
-       amdgpu_gfx_rlc_enter_safe_mode(adev);
+       amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id);
 
        if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
                def = data = RREG32_SOC15(GC, xcc_id, regRLC_CGTT_MGCG_OVERRIDE);
@@ -2238,7 +2238,7 @@ static void gfx_v9_4_3_update_coarse_grain_clock_gating(struct amdgpu_device *ad
                        WREG32_SOC15(GC, xcc_id, regRLC_CGCG_CGLS_CTRL, data);
        }
 
-       amdgpu_gfx_rlc_exit_safe_mode(adev);
+       amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id);
 }
 
 static int gfx_v9_4_3_update_gfx_clock_gating(struct amdgpu_device *adev,

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 148049782f50d9386822890237e2d14af3bfb1fc..dabeeab2f2ad875fa8f9195760aa34273aba3d2a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -629,9 +629,9 @@ static int nv_update_umd_stable_pstate(struct amdgpu_device *adev,
                                       bool enter)
 {
        if (enter)
-               amdgpu_gfx_rlc_enter_safe_mode(adev);
+               amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
        else
-               amdgpu_gfx_rlc_exit_safe_mode(adev);
+               amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
 
        if (adev->gfx.funcs->update_perfmon_mgcg)
                adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);

diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 6ef4be9322d9553cab634318c1ac689d5862b793..7d59303ca2f950a576ff22430c148a2e3e30b769 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -549,9 +549,9 @@ static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev,
                                          bool enter)
 {
        if (enter)
-               amdgpu_gfx_rlc_enter_safe_mode(adev);
+               amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
        else
-               amdgpu_gfx_rlc_exit_safe_mode(adev);
+               amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
 
        if (adev->gfx.funcs->update_perfmon_mgcg)
                adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);

diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
index f5e08b60f66ef9fa2d84bd2a86d712a839928e36..36c831b280ed9f63210e66c56de892b578693ddb 100644 (file)
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
@@ -508,19 +508,19 @@ static int kv_enable_didt(struct amdgpu_device *adev, bool enable)
            pi->caps_db_ramping ||
            pi->caps_td_ramping ||
            pi->caps_tcp_ramping) {
-               amdgpu_gfx_rlc_enter_safe_mode(adev);
+               amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
 
                if (enable) {
                        ret = kv_program_pt_config_registers(adev, didt_config_kv);
                        if (ret) {
-                               amdgpu_gfx_rlc_exit_safe_mode(adev);
+                               amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
                                return ret;
                        }
                }
 
                kv_do_enable_didt(adev, enable);
 
-               amdgpu_gfx_rlc_exit_safe_mode(adev);
+               amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
        }
 
        return 0;

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c
index 32a5a00fd8ae7a963bf7b5d18b70bb86ad0ceb68..21be23ec3c79e2f446aa4139fdf965ac252c2019 100644 (file)
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c
@@ -973,7 +973,7 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr)
            PP_CAP(PHM_PlatformCaps_TDRamping) ||
            PP_CAP(PHM_PlatformCaps_TCPRamping)) {
 
-               amdgpu_gfx_rlc_enter_safe_mode(adev);
+               amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
                mutex_lock(&adev->grbm_idx_mutex);
                value = 0;
                value2 = cgs_read_register(hwmgr->device, mmGRBM_GFX_INDEX);
@@ -1048,13 +1048,13 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr)
                }
 
                mutex_unlock(&adev->grbm_idx_mutex);
-               amdgpu_gfx_rlc_exit_safe_mode(adev);
+               amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
        }
 
        return 0;
 error:
        mutex_unlock(&adev->grbm_idx_mutex);
-       amdgpu_gfx_rlc_exit_safe_mode(adev);
+       amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
        return result;
 }
 
@@ -1068,7 +1068,7 @@ int smu7_disable_didt_config(struct pp_hwmgr *hwmgr)
            PP_CAP(PHM_PlatformCaps_TDRamping) ||
            PP_CAP(PHM_PlatformCaps_TCPRamping)) {
 
-               amdgpu_gfx_rlc_enter_safe_mode(adev);
+               amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
 
                result = smu7_enable_didt(hwmgr, false);
                PP_ASSERT_WITH_CODE((result == 0),
@@ -1081,12 +1081,12 @@ int smu7_disable_didt_config(struct pp_hwmgr *hwmgr)
                        PP_ASSERT_WITH_CODE((0 == result),
                                        "Failed to disable DPM DIDT.", goto error);
                }
-               amdgpu_gfx_rlc_exit_safe_mode(adev);
+               amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
        }
 
        return 0;
 error:
-       amdgpu_gfx_rlc_exit_safe_mode(adev);
+       amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
        return result;
 }
 

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c
index 9757d47dd6b815bfe208676b435551b830fce5ff..309a9d3bc1b790f7c1564afac43c7b0688fed2b6 100644 (file)
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c
@@ -915,7 +915,7 @@ static int vega10_enable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr)
 
        num_se = adev->gfx.config.max_shader_engines;
 
-       amdgpu_gfx_rlc_enter_safe_mode(adev);
+       amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
 
        mutex_lock(&adev->grbm_idx_mutex);
        for (count = 0; count < num_se; count++) {
@@ -940,7 +940,7 @@ static int vega10_enable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr)
 
        vega10_didt_set_mask(hwmgr, true);
 
-       amdgpu_gfx_rlc_exit_safe_mode(adev);
+       amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
 
        return 0;
 }
@@ -949,11 +949,11 @@ static int vega10_disable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr)
 {
        struct amdgpu_device *adev = hwmgr->adev;
 
-       amdgpu_gfx_rlc_enter_safe_mode(adev);
+       amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
 
        vega10_didt_set_mask(hwmgr, false);
 
-       amdgpu_gfx_rlc_exit_safe_mode(adev);
+       amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
 
        return 0;
 }
@@ -966,7 +966,7 @@ static int vega10_enable_psm_gc_didt_config(struct pp_hwmgr *hwmgr)
 
        num_se = adev->gfx.config.max_shader_engines;
 
-       amdgpu_gfx_rlc_enter_safe_mode(adev);
+       amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
 
        mutex_lock(&adev->grbm_idx_mutex);
        for (count = 0; count < num_se; count++) {
@@ -985,7 +985,7 @@ static int vega10_enable_psm_gc_didt_config(struct pp_hwmgr *hwmgr)
 
        vega10_didt_set_mask(hwmgr, true);
 
-       amdgpu_gfx_rlc_exit_safe_mode(adev);
+       amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
 
        vega10_program_gc_didt_config_registers(hwmgr, GCDiDtDroopCtrlConfig_vega10);
        if (PP_CAP(PHM_PlatformCaps_GCEDC))
@@ -1002,11 +1002,11 @@ static int vega10_disable_psm_gc_didt_config(struct pp_hwmgr *hwmgr)
        struct amdgpu_device *adev = hwmgr->adev;
        uint32_t data;
 
-       amdgpu_gfx_rlc_enter_safe_mode(adev);
+       amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
 
        vega10_didt_set_mask(hwmgr, false);
 
-       amdgpu_gfx_rlc_exit_safe_mode(adev);
+       amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
 
        if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
                data = 0x00000000;
@@ -1027,7 +1027,7 @@ static int vega10_enable_se_edc_config(struct pp_hwmgr *hwmgr)
 
        num_se = adev->gfx.config.max_shader_engines;
 
-       amdgpu_gfx_rlc_enter_safe_mode(adev);
+       amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
 
        mutex_lock(&adev->grbm_idx_mutex);
        for (count = 0; count < num_se; count++) {
@@ -1048,7 +1048,7 @@ static int vega10_enable_se_edc_config(struct pp_hwmgr *hwmgr)
 
        vega10_didt_set_mask(hwmgr, true);
 
-       amdgpu_gfx_rlc_exit_safe_mode(adev);
+       amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
 
        return 0;
 }
@@ -1057,11 +1057,11 @@ static int vega10_disable_se_edc_config(struct pp_hwmgr *hwmgr)
 {
        struct amdgpu_device *adev = hwmgr->adev;
 
-       amdgpu_gfx_rlc_enter_safe_mode(adev);
+       amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
 
        vega10_didt_set_mask(hwmgr, false);
 
-       amdgpu_gfx_rlc_exit_safe_mode(adev);
+       amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
 
        return 0;
 }
@@ -1075,7 +1075,7 @@ static int vega10_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)
 
        num_se = adev->gfx.config.max_shader_engines;
 
-       amdgpu_gfx_rlc_enter_safe_mode(adev);
+       amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
 
        vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10);
 
@@ -1096,7 +1096,7 @@ static int vega10_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)
 
        vega10_didt_set_mask(hwmgr, true);
 
-       amdgpu_gfx_rlc_exit_safe_mode(adev);
+       amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
 
        vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCDroopCtrlConfig_vega10);
 
@@ -1116,11 +1116,11 @@ static int vega10_disable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)
        struct amdgpu_device *adev = hwmgr->adev;
        uint32_t data;
 
-       amdgpu_gfx_rlc_enter_safe_mode(adev);
+       amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
 
        vega10_didt_set_mask(hwmgr, false);
 
-       amdgpu_gfx_rlc_exit_safe_mode(adev);
+       amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
 
        if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
                data = 0x00000000;
@@ -1138,7 +1138,7 @@ static int vega10_enable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr)
        struct amdgpu_device *adev = hwmgr->adev;
        int result;
 
-       amdgpu_gfx_rlc_enter_safe_mode(adev);
+       amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
 
        mutex_lock(&adev->grbm_idx_mutex);
        WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
@@ -1151,7 +1151,7 @@ static int vega10_enable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr)
 
        vega10_didt_set_mask(hwmgr, false);
 
-       amdgpu_gfx_rlc_exit_safe_mode(adev);
+       amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
 
        return 0;
 }