arm64: dts: ti: k3-j721e: Add overlay to enable CPSW9G ports in QSGMII mode

The J7 Quad Port Add-On Ethernet Card for J721E Common-Proc-Board supports
QSGMII mode. Use the overlay to configure CPSW9G ports in QSGMII mode.

Add support to reset the PHY from kernel by using gpio-hog and gpio-reset.

Add aliases for CPSW9G ports to enable kernel to fetch MAC addresses
directly from U-Boot.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230315062307.1612220-3-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 6acd12409d59b79839332f98e45dcdfb128395bc..7ded6dacd3f25ec0ae971549305ceeaff0b8047b 100644 (file)
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -31,8 +31,9 @@ dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb
 
 # Boards with J721e SoC
+k3-j721e-evm-dtbs := k3-j721e-common-proc-board.dtb k3-j721e-evm-quad-port-eth-exp.dtbo
 dtb-$(CONFIG_ARCH_K3) += k3-j721e-beagleboneai64.dtb
-dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb
 
 # Boards with J721s2 SoC

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso b/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso
new file mode 100644 (file)
index 0000000..6ff7b6a
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
+ * J721E board.
+ *
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/mux/ti-serdes.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/phy/phy-cadence.h>
+
+#include "k3-pinctrl.h"
+
+&{/} {
+       aliases {
+               ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
+               ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
+               ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
+               ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
+       };
+};
+
+&cpsw0 {
+       status = "okay";
+};
+
+&cpsw0_port1 {
+       status = "okay";
+       phy-handle = <&cpsw9g_phy0>;
+       phy-mode = "qsgmii";
+       mac-address = [00 00 00 00 00 00];
+       phys = <&cpsw0_phy_gmii_sel 1>;
+};
+
+&cpsw0_port2 {
+       status = "okay";
+       phy-handle = <&cpsw9g_phy1>;
+       phy-mode = "qsgmii";
+       mac-address = [00 00 00 00 00 00];
+       phys = <&cpsw0_phy_gmii_sel 2>;
+};
+
+&cpsw0_port3 {
+       status = "okay";
+       phy-handle = <&cpsw9g_phy2>;
+       phy-mode = "qsgmii";
+       mac-address = [00 00 00 00 00 00];
+       phys = <&cpsw0_phy_gmii_sel 3>;
+};
+
+&cpsw0_port4 {
+       status = "okay";
+       phy-handle = <&cpsw9g_phy3>;
+       phy-mode = "qsgmii";
+       mac-address = [00 00 00 00 00 00];
+       phys = <&cpsw0_phy_gmii_sel 4>;
+};
+
+&cpsw9g_mdio {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&mdio0_pins_default>;
+       reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>;
+       reset-post-delay-us = <120000>;
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       cpsw9g_phy0: ethernet-phy@17 {
+               reg = <17>;
+       };
+       cpsw9g_phy1: ethernet-phy@16 {
+               reg = <16>;
+       };
+       cpsw9g_phy2: ethernet-phy@18 {
+               reg = <18>;
+       };
+       cpsw9g_phy3: ethernet-phy@19 {
+               reg = <19>;
+       };
+};
+
+&exp2 {
+       qsgmii-line-hog {
+               gpio-hog;
+               gpios = <16 GPIO_ACTIVE_HIGH>;
+               output-low;
+               line-name = "qsgmii-pwrdn-line";
+       };
+};
+
+&main_pmx0 {
+       mdio0_pins_default: mdio0-pins-default {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */
+                       J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */
+               >;
+       };
+};
+
+&serdes_ln_ctrl {
+       idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_QSGMII_LANE2>,
+                     <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
+                     <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
+                     <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
+                     <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
+                     <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
+};
+
+&serdes_wiz0 {
+       status = "okay";
+};
+
+&serdes0 {
+       status = "okay";
+
+       assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
+       assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       serdes0_qsgmii_link: phy@1 {
+               reg = <1>;
+               cdns,num-lanes = <1>;
+               #phy-cells = <0>;
+               cdns,phy-type = <PHY_TYPE_QSGMII>;
+               resets = <&serdes_wiz0 2>;
+       };
+};