arm64: dts: renesas: ebisu, draak: Limit EtherAVB to 100Mbps

* According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of
  August 24, 2018, the TX clock internal delay mode isn't supported
  on R-Car E3 (r8a77990) and D3 (r8a77995).

* TX clock internal delay mode is required for reliable 1Gbps communication
  using the KSZ9031RNX phy present on the Ebisu and Draak boards.

Thus, the E3 based Ebisu and D3 based Draak boards can not reliably
use 1Gbps and the speed should be limited to 100Mbps.

Based on work by Kazuya Mizuguchi.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
index 81db803f43891c6d2f06f344ec5308069525bec8..b38f9d442fc08f2c7e5a606e0ddc8fe9ac6dfd78 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
@@ -271,6 +271,14 @@
                interrupt-parent = <&gpio2>;
                interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
                reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
+               /*
+                * TX clock internal delay mode is required for reliable
+                * 1Gbps communication using the KSZ9031RNX phy present on
+                * the Ebisu board, however, TX clock internal delay mode
+                * isn't supported on r8a77990.  Thus, limit speed to
+                * 100Mbps for reliable communication.
+                */
+               max-speed = <100>;
        };
 };
 

diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
index fe14792cedfb08b94f6a76935e2b168c0ded0bfe..0bbd4d70104260acfdbf2f73deeb286f1fdd4317 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
@@ -175,6 +175,14 @@
                reg = <0>;
                interrupt-parent = <&gpio5>;
                interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+               /*
+                * TX clock internal delay mode is required for reliable
+                * 1Gbps communication using the KSZ9031RNX phy present on
+                * the Draak board, however, TX clock internal delay mode
+                * isn't supported on r8a77995.  Thus, limit speed to
+                * 100Mbps for reliable communication.
+                */
+               max-speed = <100>;
        };
 };