iommu/vt-d: Add PASID_FLAG_FL5LP for first-level pasid setup

Current intel_pasid_setup_first_level() use 5-level paging for
first level translation if CPUs use 5-level paging mode too.
This makes sense for SVA usages since the page table is shared
between CPUs and IOMMUs. But it makes no sense if we only want
to use first level for IOVA translation. Add PASID_FLAG_FL5LP
bit in the flags which indicates whether the 5-level paging
mode should be used.

Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>

diff --git a/drivers/iommu/intel-pasid.c b/drivers/iommu/intel-pasid.c
index 3cb569e76642358028a6cef3f43e508b9e4e2c4e..22b30f10b3964e9d59a9a10d9abc8f35b75e59e8 100644 (file)
--- a/drivers/iommu/intel-pasid.c
+++ b/drivers/iommu/intel-pasid.c
@@ -477,18 +477,15 @@ int intel_pasid_setup_first_level(struct intel_iommu *iommu,
                pasid_set_sre(pte);
        }
 
-#ifdef CONFIG_X86
-       /* Both CPU and IOMMU paging mode need to match */
-       if (cpu_feature_enabled(X86_FEATURE_LA57)) {
+       if (flags & PASID_FLAG_FL5LP) {
                if (cap_5lp_support(iommu->cap)) {
                        pasid_set_flpm(pte, 1);
                } else {
-                       pr_err("VT-d has no 5-level paging support for CPU\n");
+                       pr_err("No 5-level paging support for first-level\n");
                        pasid_clear_entry(pte);
                        return -EINVAL;
                }
        }
-#endif /* CONFIG_X86 */
 
        pasid_set_domain_id(pte, did);
        pasid_set_address_width(pte, iommu->agaw);

diff --git a/drivers/iommu/intel-pasid.h b/drivers/iommu/intel-pasid.h
index fc8cd8f17de166a8c96c82c3e73b3e1c3f1572d0..92de6df24ccb10d136d003a88c79eb001fab2892 100644 (file)
--- a/drivers/iommu/intel-pasid.h
+++ b/drivers/iommu/intel-pasid.h
@@ -37,6 +37,12 @@
  */
 #define PASID_FLAG_SUPERVISOR_MODE     BIT(0)
 
+/*
+ * The PASID_FLAG_FL5LP flag Indicates using 5-level paging for first-
+ * level translation, otherwise, 4-level paging will be used.
+ */
+#define PASID_FLAG_FL5LP               BIT(1)
+
 struct pasid_dir_entry {
        u64 val;
 };

diff --git a/drivers/iommu/intel-svm.c b/drivers/iommu/intel-svm.c
index 04023033b79f4c9bae238ed00c10bf28e7918091..d7f2a53589002e6aee3bdcf43bc8132c20415092 100644 (file)
--- a/drivers/iommu/intel-svm.c
+++ b/drivers/iommu/intel-svm.c
@@ -364,7 +364,9 @@ int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_
                ret = intel_pasid_setup_first_level(iommu, dev,
                                mm ? mm->pgd : init_mm.pgd,
                                svm->pasid, FLPT_DEFAULT_DID,
-                               mm ? 0 : PASID_FLAG_SUPERVISOR_MODE);
+                               (mm ? 0 : PASID_FLAG_SUPERVISOR_MODE) |
+                               (cpu_feature_enabled(X86_FEATURE_LA57) ?
+                                PASID_FLAG_FL5LP : 0));
                spin_unlock(&iommu->lock);
                if (ret) {
                        if (mm)
@@ -385,7 +387,9 @@ int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_
                ret = intel_pasid_setup_first_level(iommu, dev,
                                                mm ? mm->pgd : init_mm.pgd,
                                                svm->pasid, FLPT_DEFAULT_DID,
-                                               mm ? 0 : PASID_FLAG_SUPERVISOR_MODE);
+                                               (mm ? 0 : PASID_FLAG_SUPERVISOR_MODE) |
+                                               (cpu_feature_enabled(X86_FEATURE_LA57) ?
+                                               PASID_FLAG_FL5LP : 0));
                spin_unlock(&iommu->lock);
                if (ret) {
                        kfree(sdev);