clk: qcom: rpmh: Add support for X1E80100 rpmh clocks

Adds the RPMH clocks present in X1E80100 SoC

Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231205061002.30759-5-quic_sibis@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
index bb09170600ec4f6f736e08a3b7a6e47adac8b6ec..bb82abeed88f3bbc49d08fa192ea3e3ac0ac6286 100644 (file)
--- a/drivers/clk/qcom/clk-rpmh.c
+++ b/drivers/clk/qcom/clk-rpmh.c
@@ -372,6 +372,7 @@ DEFINE_CLK_RPMH_VRM(clk3, _a1, "clka3", 1);
 DEFINE_CLK_RPMH_VRM(clk4, _a1, "clka4", 1);
 DEFINE_CLK_RPMH_VRM(clk5, _a1, "clka5", 1);
 
+DEFINE_CLK_RPMH_VRM(clk3, _a2, "clka3", 2);
 DEFINE_CLK_RPMH_VRM(clk4, _a2, "clka4", 2);
 DEFINE_CLK_RPMH_VRM(clk5, _a2, "clka5", 2);
 DEFINE_CLK_RPMH_VRM(clk6, _a2, "clka6", 2);
@@ -770,6 +771,28 @@ static const struct clk_rpmh_desc clk_rpmh_sm4450 = {
        .num_clks = ARRAY_SIZE(sm4450_rpmh_clocks),
 };
 
+static struct clk_hw *x1e80100_rpmh_clocks[] = {
+       [RPMH_CXO_CLK]          = &clk_rpmh_bi_tcxo_div2.hw,
+       [RPMH_CXO_CLK_A]        = &clk_rpmh_bi_tcxo_div2_ao.hw,
+       [RPMH_LN_BB_CLK1]       = &clk_rpmh_clk6_a2.hw,
+       [RPMH_LN_BB_CLK1_A]     = &clk_rpmh_clk6_a2_ao.hw,
+       [RPMH_LN_BB_CLK2]       = &clk_rpmh_clk7_a2.hw,
+       [RPMH_LN_BB_CLK2_A]     = &clk_rpmh_clk7_a2_ao.hw,
+       [RPMH_LN_BB_CLK3]       = &clk_rpmh_clk8_a2.hw,
+       [RPMH_LN_BB_CLK3_A]     = &clk_rpmh_clk8_a2_ao.hw,
+       [RPMH_RF_CLK3]          = &clk_rpmh_clk3_a2.hw,
+       [RPMH_RF_CLK3_A]        = &clk_rpmh_clk3_a2_ao.hw,
+       [RPMH_RF_CLK4]          = &clk_rpmh_clk4_a2.hw,
+       [RPMH_RF_CLK4_A]        = &clk_rpmh_clk4_a2_ao.hw,
+       [RPMH_RF_CLK5]          = &clk_rpmh_clk5_a2.hw,
+       [RPMH_RF_CLK5_A]        = &clk_rpmh_clk5_a2_ao.hw,
+};
+
+static const struct clk_rpmh_desc clk_rpmh_x1e80100 = {
+       .clks = x1e80100_rpmh_clocks,
+       .num_clks = ARRAY_SIZE(x1e80100_rpmh_clocks),
+};
+
 static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
                                         void *data)
 {
@@ -872,6 +895,7 @@ static const struct of_device_id clk_rpmh_match_table[] = {
        { .compatible = "qcom,sm8550-rpmh-clk", .data = &clk_rpmh_sm8550},
        { .compatible = "qcom,sm8650-rpmh-clk", .data = &clk_rpmh_sm8650},
        { .compatible = "qcom,sc7280-rpmh-clk", .data = &clk_rpmh_sc7280},
+       { .compatible = "qcom,x1e80100-rpmh-clk", .data = &clk_rpmh_x1e80100},
        { }
 };
 MODULE_DEVICE_TABLE(of, clk_rpmh_match_table);