bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
/*
- * If the buffer address is not DMA-able, len is not long enough to make
- * DMA transfers profitable or panic_write() may be in an interrupt
- * context fallback to PIO mode.
+ * If the buffer address is not DMA-able, len is not long enough to
+ * make DMA transfers profitable or if invoked from panic_write()
+ * fallback to PIO mode.
*/
if (!virt_addr_valid(buf) || bram_offset & 3 || (size_t)buf & 3 ||
- count < 384 || in_interrupt() || oops_in_progress)
+ count < 384 || mtd->oops_panic_write)
goto out_copy;
xtra = count & 3;
bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
/*
- * If the buffer address is not DMA-able, len is not long enough to make
- * DMA transfers profitable or panic_write() may be in an interrupt
- * context fallback to PIO mode.
+ * If the buffer address is not DMA-able, len is not long enough to
+ * make DMA transfers profitable or if invoked from panic_write()
+ * fallback to PIO mode.
*/
if (!virt_addr_valid(buf) || bram_offset & 3 || (size_t)buf & 3 ||
- count < 384 || in_interrupt() || oops_in_progress)
+ count < 384 || mtd->oops_panic_write)
goto out_copy;
dma_src = dma_map_single(dev, buf, count, DMA_TO_DEVICE);
*/
void nand_wait_ready(struct nand_chip *chip)
{
+ struct mtd_info *mtd = nand_to_mtd(chip);
unsigned long timeo = 400;
- if (in_interrupt() || oops_in_progress)
+ if (mtd->oops_panic_write)
return panic_nand_wait_ready(chip, timeo);
/* Wait until command is processed or timeout occurs */
*/
static int nand_wait(struct nand_chip *chip)
{
-
+ struct mtd_info *mtd = nand_to_mtd(chip);
unsigned long timeo = 400;
u8 status;
int ret;
if (ret)
return ret;
- if (in_interrupt() || oops_in_progress)
+ if (mtd->oops_panic_write) {
panic_nand_wait(chip, timeo);
- else {
+ } else {
timeo = jiffies + msecs_to_jiffies(timeo);
do {
if (chip->legacy.dev_ready) {