target-arm queue:
* remove a line of redundant code
* convert various TCG helper fns to use 'fpst' alias
* Use float_status in helper_fcvtx_f64_to_f32
* Use float_status in helper_vfp_fcvt{ds,sd}
* Implement FEAT_XS
* hw/intc/arm_gicv3_its: Zero initialize local DTEntry etc structs
* tests/functional: update sbsa-ref firmware used in test
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# gpg: Signature made Tue 17 Dec 2024 12:17:49 EST
# gpg: using RSA key
E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-
20241217' of https://git.linaro.org/people/pmaydell/qemu-arm:
tests/functional: update sbsa-ref firmware used in test
hw/intc/arm_gicv3_its: Zero initialize local DTEntry etc structs
tests/tcg/aarch64: add system test for FEAT_XS
target/arm: Enable FEAT_XS for the max cpu
target/arm: Add decodetree entry for DSB nXS variant
target/arm: Add ARM_CP_ADD_TLBI_NXS type flag to TLBI insns
target/arm: Add ARM_CP_ADD_TLBI_NXS type flag for NXS insns
target/arm: Implement fine-grained-trap handling for FEAT_XS
target/arm: Use float_status in helper_vfp_fcvt{ds,sd}
target/arm: Use float_status in helper_fcvtx_f64_to_f32
target/arm: Convert neon_helper.c to use env alias
target/arm: Convert vec_helper.c to use env alias
target/arm: Convert sme_helper.c to fpst alias
target/arm: Convert sve_helper.c to fpst alias
target/arm: Convert neon_helper.c to fpst alias
target/arm: Convert vec_helper.c to fpst alias
target/arm: Convert helper-a64.c to fpst alias
target/arm: Convert vfp_helper.c to fpst alias
target/arm: remove redundant code
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>