arm64: dts: rockchip: Add clk_rtc_32k to Anbernic xx3 Devices

For the Anbernic devices to display properly, we need to specify the
clock frequency of the PLL_VPLL. Adding the parent clock in the
rk356x.dtsi requires us to update our clock definitions to accomplish
this.

Fixes: 64b69474edf3 ("arm64: dts: rockchip: assign rate to clk_rtc_32k on rk356x")
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Link: https://lore.kernel.org/r/20230327153547.821822-1-macroalpha82@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353x.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353x.dtsi
index 65a80d1f6d911a5d400d57502c61da5f56581d00..9a0e217f069ff1a8ecdb75c5903f6407a1dfc708 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353x.dtsi
@@ -16,8 +16,10 @@
 };
 
 &cru {
-       assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
-       assigned-clock-rates = <1200000000>, <200000000>, <241500000>;
+       assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
+                         <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
+       assigned-clock-rates = <32768>, <1200000000>,
+                              <200000000>, <241500000>;
 };
 
 &gpio_keys_control {

diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts
index b4b2df821cba90412ad7a60e5752b2590ddb23b4..c763c7f3b1b38b71fc1702c1e6a157d58e6af2e8 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts
@@ -105,8 +105,10 @@
 };
 
 &cru {
-       assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
-       assigned-clock-rates = <1200000000>, <200000000>, <500000000>;
+       assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
+                         <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
+       assigned-clock-rates = <32768>, <1200000000>,
+                              <200000000>, <500000000>;
 };
 
 &dsi_dphy0 {