drm/amd/display: Disable DWB frame capture to emulate oneshot

[WHY]
drm_writeback requires to capture exact one frame in each writeback
call.

[HOW]
frame_capture is disabled after each writeback is completed.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 7e5e4be99b6000ea042862c53a1a26306cebdfea..6aabe8a3ffef19d3904ec5c0237ae33f4d812c61 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -595,8 +595,20 @@ static void dm_crtc_high_irq(void *interrupt_params)
                                                       list_entry);
                        spin_unlock_irqrestore(&acrtc->wb_conn->job_lock, flags);
 
-                       if (job)
+                       if (job) {
+                               unsigned int v_total, refresh_hz;
+                               struct dc_stream_state *stream = acrtc->dm_irq_params.stream;
+
+                               v_total = stream->adjust.v_total_max ?
+                                         stream->adjust.v_total_max : stream->timing.v_total;
+                               refresh_hz = div_u64((uint64_t) stream->timing.pix_clk_100hz *
+                                            100LL, (v_total * stream->timing.h_total));
+                               mdelay(1000 / refresh_hz);
+
                                drm_writeback_signal_completion(acrtc->wb_conn, 0);
+                               dc_stream_fc_disable_writeback(adev->dm.dc,
+                                                              acrtc->dm_irq_params.stream, 0);
+                       }
                } else
                        DRM_ERROR("%s: no amdgpu_crtc wb_conn\n", __func__);
                acrtc->wb_pending = false;

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 3dd9f4ab2261f5d43761ffeee1d11ae93551c3ae..38cd29b210c05477f9873526eb1352dc0915695c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -489,6 +489,33 @@ bool dc_stream_add_writeback(struct dc *dc,
        return true;
 }
 
+bool dc_stream_fc_disable_writeback(struct dc *dc,
+               struct dc_stream_state *stream,
+               uint32_t dwb_pipe_inst)
+{
+       struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst];
+
+       if (stream == NULL) {
+               dm_error("DC: dc_stream is NULL!\n");
+               return false;
+       }
+
+       if (dwb_pipe_inst >= MAX_DWB_PIPES) {
+               dm_error("DC: writeback pipe is invalid!\n");
+               return false;
+       }
+
+       if (stream->num_wb_info > MAX_DWB_PIPES) {
+               dm_error("DC: num_wb_info is invalid!\n");
+               return false;
+       }
+
+       if (dwb->funcs->set_fc_enable)
+               dwb->funcs->set_fc_enable(dwb, DWB_FRAME_CAPTURE_DISABLE);
+
+       return true;
+}
+
 bool dc_stream_remove_writeback(struct dc *dc,
                struct dc_stream_state *stream,
                uint32_t dwb_pipe_inst)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index e61eea6db29cd50e73fc88180537b0884a1927f2..4ac48c346a3399d510844195fdee3897a1999029 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -454,6 +454,10 @@ bool dc_stream_add_writeback(struct dc *dc,
                struct dc_stream_state *stream,
                struct dc_writeback_info *wb_info);
 
+bool dc_stream_fc_disable_writeback(struct dc *dc,
+               struct dc_stream_state *stream,
+               uint32_t dwb_pipe_inst);
+
 bool dc_stream_remove_writeback(struct dc *dc,
                struct dc_stream_state *stream,
                uint32_t dwb_pipe_inst);