mmc: renesas_sdhi: enable WAIT_WHILE_BUSY
authorWolfram Sang <wsa+renesas@sang-engineering.com>
Fri, 9 Apr 2021 09:46:06 +0000 (11:46 +0200)
committerUlf Hansson <ulf.hansson@linaro.org>
Mon, 12 Apr 2021 11:52:47 +0000 (13:52 +0200)
Now that we got the timeout handling in the driver correct, we can use
this capability to avoid polling via the MMC core.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20210409094606.4317-1-wsa+renesas@sang-engineering.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
drivers/mmc/host/renesas_sdhi_internal_dmac.c
drivers/mmc/host/renesas_sdhi_sys_dmac.c

index ff97f15e317cc1654b94639c29a35f99ff4b39b9..e8f4863d8f1a6e019ec0c05d257813f2c887df95 100644 (file)
@@ -97,7 +97,7 @@ static const struct renesas_sdhi_of_data of_rza2_compatible = {
                          TMIO_MMC_HAVE_CBSY,
        .tmio_ocr_mask  = MMC_VDD_32_33,
        .capabilities   = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
-                         MMC_CAP_CMD23,
+                         MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY,
        .bus_shift      = 2,
        .scc_offset     = 0 - 0x1000,
        .taps           = rcar_gen3_scc_taps,
@@ -111,7 +111,7 @@ static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
                          TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
        .capabilities   = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
-                         MMC_CAP_CMD23,
+                         MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY,
        .capabilities2  = MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE,
        .bus_shift      = 2,
        .scc_offset     = 0x1000,
index c5f7896753028f3d75b77e8006269ce8f3a36764..ffa64211f4deb7605382a36c93f79128a51c4afb 100644 (file)
@@ -33,12 +33,14 @@ static const struct renesas_sdhi_of_data of_rz_compatible = {
        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_32BIT_DATA_PORT |
                          TMIO_MMC_HAVE_CBSY,
        .tmio_ocr_mask  = MMC_VDD_32_33,
-       .capabilities   = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
+       .capabilities   = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
+                         MMC_CAP_WAIT_WHILE_BUSY,
 };
 
 static const struct renesas_sdhi_of_data of_rcar_gen1_compatible = {
        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL,
-       .capabilities   = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
+       .capabilities   = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
+                         MMC_CAP_WAIT_WHILE_BUSY,
        .capabilities2  = MMC_CAP2_NO_WRITE_PROTECT,
 };
 
@@ -58,7 +60,7 @@ static const struct renesas_sdhi_of_data of_rcar_gen2_compatible = {
        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
                          TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
        .capabilities   = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
-                         MMC_CAP_CMD23,
+                         MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY,
        .capabilities2  = MMC_CAP2_NO_WRITE_PROTECT,
        .dma_buswidth   = DMA_SLAVE_BUSWIDTH_4_BYTES,
        .dma_rx_offset  = 0x2000,