x86/cpu: Fix Gracemont uarch
authorPeter Zijlstra <peterz@infradead.org>
Mon, 7 Aug 2023 12:38:07 +0000 (14:38 +0200)
committerPeter Zijlstra <peterz@infradead.org>
Wed, 9 Aug 2023 19:51:06 +0000 (21:51 +0200)
Alderlake N is an E-core only product using Gracemont
micro-architecture. It fits the pre-existing naming scheme perfectly
fine, adhere to it.

Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Link: https://lore.kernel.org/r/20230807150405.686834933@infradead.org
14 files changed:
arch/x86/events/intel/core.c
arch/x86/events/intel/cstate.c
arch/x86/events/intel/uncore.c
arch/x86/events/msr.c
arch/x86/events/rapl.c
arch/x86/include/asm/intel-family.h
arch/x86/kernel/cpu/intel_epb.c
arch/x86/mm/init.c
drivers/idle/intel_idle.c
drivers/platform/x86/intel/pmc/core.c
drivers/powercap/intel_rapl_common.c
drivers/powercap/intel_rapl_msr.c
drivers/thermal/intel/intel_tcc_cooling.c
tools/power/x86/turbostat/turbostat.c

index a149fafad813dfcd9e8bab5f3639284fbfec1032..c7e7ed6814ef97829bac213a95ef07d5af7ca417 100644 (file)
@@ -6167,7 +6167,7 @@ __init int intel_pmu_init(void)
                name = "Tremont";
                break;
 
-       case INTEL_FAM6_ALDERLAKE_N:
+       case INTEL_FAM6_ATOM_GRACEMONT:
                x86_pmu.mid_ack = true;
                memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
                       sizeof(hw_cache_event_ids));
index 97035db68df208052883fe3ba65a3a75789b9ddb..96fffb2d521d2a992f02eed7ce072daba22764c9 100644 (file)
@@ -669,6 +669,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
        X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D,      &glm_cstates),
        X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT,        &glm_cstates),
        X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L,      &glm_cstates),
+       X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT,      &adl_cstates),
 
        X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L,           &icl_cstates),
        X86_MATCH_INTEL_FAM6_MODEL(ICELAKE,             &icl_cstates),
@@ -684,7 +685,6 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
        X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE,          &icl_cstates),
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,           &adl_cstates),
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,         &adl_cstates),
-       X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N,         &adl_cstates),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE,          &adl_cstates),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P,        &adl_cstates),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S,        &adl_cstates),
index bc226603ef3ef188cd9cb5540e13916dcf99ef5e..69043e02e8a7d828ec2f096ba940648c5c3f39ea 100644 (file)
@@ -1858,7 +1858,6 @@ static const struct x86_cpu_id intel_uncore_match[] __initconst = {
        X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE,          &rkl_uncore_init),
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,           &adl_uncore_init),
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,         &adl_uncore_init),
-       X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N,         &adl_uncore_init),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE,          &adl_uncore_init),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P,        &adl_uncore_init),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S,        &adl_uncore_init),
@@ -1867,6 +1866,7 @@ static const struct x86_cpu_id intel_uncore_match[] __initconst = {
        X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X,    &spr_uncore_init),
        X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X,     &spr_uncore_init),
        X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D,      &snr_uncore_init),
+       X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT,      &adl_uncore_init),
        {},
 };
 MODULE_DEVICE_TABLE(x86cpu, intel_uncore_match);
index 61c59e0627d46644e2b436fab4ef5f0d191e5bd1..9e237b30f01745f9f869c34384496c990011d2c7 100644 (file)
@@ -106,7 +106,7 @@ static bool test_intel(int idx, void *data)
        case INTEL_FAM6_ROCKETLAKE:
        case INTEL_FAM6_ALDERLAKE:
        case INTEL_FAM6_ALDERLAKE_L:
-       case INTEL_FAM6_ALDERLAKE_N:
+       case INTEL_FAM6_ATOM_GRACEMONT:
        case INTEL_FAM6_RAPTORLAKE:
        case INTEL_FAM6_RAPTORLAKE_P:
        case INTEL_FAM6_RAPTORLAKE_S:
index 52e6e7ed4f78a655414ce1b7548c8f0b7d5d8822..1579429846ccf928f2a9b6fd54ef21f109c9c173 100644 (file)
@@ -804,7 +804,7 @@ static const struct x86_cpu_id rapl_model_match[] __initconst = {
        X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE,           &model_skl),
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,           &model_skl),
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,         &model_skl),
-       X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N,         &model_skl),
+       X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT,      &model_skl),
        X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X,    &model_spr),
        X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X,     &model_spr),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE,          &model_skl),
index b3af2d45bbbb58424e2d34b3887d836470d80d21..40413262b4cc843b8320ec5dcef1b65642f11071 100644 (file)
 
 #define INTEL_FAM6_ALDERLAKE           0x97    /* Golden Cove / Gracemont */
 #define INTEL_FAM6_ALDERLAKE_L         0x9A    /* Golden Cove / Gracemont */
-#define INTEL_FAM6_ALDERLAKE_N         0xBE
 
 #define INTEL_FAM6_RAPTORLAKE          0xB7
 #define INTEL_FAM6_RAPTORLAKE_P                0xBA
 #define INTEL_FAM6_ATOM_TREMONT                0x96 /* Elkhart Lake */
 #define INTEL_FAM6_ATOM_TREMONT_L      0x9C /* Jasper Lake */
 
+#define INTEL_FAM6_ATOM_GRACEMONT      0xBE /* Alderlake N */
+
 #define INTEL_FAM6_SIERRAFOREST_X      0xAF
 
 #define INTEL_FAM6_GRANDRIDGE          0xB6
index 3b8476158236c358d50cdb0f3f3eb5aed2817918..e4c3ba91321c95ad601d8e29f7439ab803c315a9 100644 (file)
@@ -206,7 +206,7 @@ static int intel_epb_offline(unsigned int cpu)
 static const struct x86_cpu_id intel_epb_normal[] = {
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,
                                   ENERGY_PERF_BIAS_NORMAL_POWERSAVE),
-       X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N,
+       X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT,
                                   ENERGY_PERF_BIAS_NORMAL_POWERSAVE),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P,
                                   ENERGY_PERF_BIAS_NORMAL_POWERSAVE),
index 8192452d1d2d3569dddfb109e74e6b83d8b5570d..ad207f3cf4d19c33ea18bb9c297413de1bec10f9 100644 (file)
@@ -273,7 +273,7 @@ static void __init probe_page_size_mask(void)
 static const struct x86_cpu_id invlpg_miss_ids[] = {
        INTEL_MATCH(INTEL_FAM6_ALDERLAKE   ),
        INTEL_MATCH(INTEL_FAM6_ALDERLAKE_L ),
-       INTEL_MATCH(INTEL_FAM6_ALDERLAKE_N ),
+       INTEL_MATCH(INTEL_FAM6_ATOM_GRACEMONT ),
        INTEL_MATCH(INTEL_FAM6_RAPTORLAKE  ),
        INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_P),
        INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_S),
index b930036edbbef6f7fc202c262873b0f85d3fede1..46c6de321c5029c0ad7f23a71b7eca5732867f3c 100644 (file)
@@ -960,7 +960,7 @@ static struct cpuidle_state adl_l_cstates[] __initdata = {
                .enter = NULL }
 };
 
-static struct cpuidle_state adl_n_cstates[] __initdata = {
+static struct cpuidle_state gmt_cstates[] __initdata = {
        {
                .name = "C1",
                .desc = "MWAIT 0x00",
@@ -1405,8 +1405,8 @@ static const struct idle_cpu idle_cpu_adl_l __initconst = {
        .state_table = adl_l_cstates,
 };
 
-static const struct idle_cpu idle_cpu_adl_n __initconst = {
-       .state_table = adl_n_cstates,
+static const struct idle_cpu idle_cpu_gmt __initconst = {
+       .state_table = gmt_cstates,
 };
 
 static const struct idle_cpu idle_cpu_spr __initconst = {
@@ -1479,7 +1479,7 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = {
        X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D,           &idle_cpu_icx),
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,           &idle_cpu_adl),
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,         &idle_cpu_adl_l),
-       X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N,         &idle_cpu_adl_n),
+       X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT,      &idle_cpu_gmt),
        X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X,    &idle_cpu_spr),
        X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X,     &idle_cpu_spr),
        X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL,        &idle_cpu_knl),
@@ -1979,7 +1979,7 @@ static void __init intel_idle_init_cstates_icpu(struct cpuidle_driver *drv)
                break;
        case INTEL_FAM6_ALDERLAKE:
        case INTEL_FAM6_ALDERLAKE_L:
-       case INTEL_FAM6_ALDERLAKE_N:
+       case INTEL_FAM6_ATOM_GRACEMONT:
                adl_idle_state_table_update();
                break;
        }
index 5a36b3f77bc57292e1a4fabc0f5314a343f01947..84c175b9721a0b9af97f4ea2390f58a06c479294 100644 (file)
@@ -1123,7 +1123,7 @@ static const struct x86_cpu_id intel_pmc_core_ids[] = {
        X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L,      icl_core_init),
        X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE,          tgl_core_init),
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,         tgl_core_init),
-       X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N,         tgl_core_init),
+       X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT,      tgl_core_init),
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,           adl_core_init),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P,        tgl_core_init),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE,          adl_core_init),
index 4e646e5e48f6800535817b0ba34499d148fa1ebf..a942a2527a9a9849e7161bf6e8907161eed28dc7 100644 (file)
@@ -1250,7 +1250,7 @@ static const struct x86_cpu_id rapl_ids[] __initconst = {
        X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE,          &rapl_defaults_core),
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,           &rapl_defaults_core),
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,         &rapl_defaults_core),
-       X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N,         &rapl_defaults_core),
+       X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT,      &rapl_defaults_core),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE,          &rapl_defaults_core),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P,        &rapl_defaults_core),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S,        &rapl_defaults_core),
index 569e25eab1e1b6e4da8cde85fb1a2f774e663214..1e775b0db21115352aa705759930e16f57efb35d 100644 (file)
@@ -141,7 +141,7 @@ static const struct x86_cpu_id pl4_support_ids[] = {
        X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, NULL),
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, NULL),
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, NULL),
-       X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N, NULL),
+       X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT, NULL),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, NULL),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, NULL),
        X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE, NULL),
index e95f799454fe2dbe8f0402c3128a22f6608257f9..6c392147e6d1c99f134cddcd501e9d07798c312a 100644 (file)
@@ -60,7 +60,7 @@ static const struct x86_cpu_id tcc_ids[] __initconst = {
        X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE, NULL),
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, NULL),
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, NULL),
-       X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N, NULL),
+       X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT, NULL),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, NULL),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, NULL),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S, NULL),
index 8a36ba5df9f90a0dc7c5ecd52b929de4d7b9eafb..9a10512e340787decdeee31ca29b740d02e16ee2 100644 (file)
@@ -5447,7 +5447,7 @@ unsigned int intel_model_duplicates(unsigned int model)
        case INTEL_FAM6_LAKEFIELD:
        case INTEL_FAM6_ALDERLAKE:
        case INTEL_FAM6_ALDERLAKE_L:
-       case INTEL_FAM6_ALDERLAKE_N:
+       case INTEL_FAM6_ATOM_GRACEMONT:
        case INTEL_FAM6_RAPTORLAKE:
        case INTEL_FAM6_RAPTORLAKE_P:
        case INTEL_FAM6_RAPTORLAKE_S: