&xlat, &sz, full->attrs, &prot);
assert(sz >= TARGET_PAGE_SIZE);
- tlb_debug("vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx
+ tlb_debug("vaddr=" TARGET_FMT_lx " paddr=0x" HWADDR_FMT_plx
" prot=%x idx=%d\n",
vaddr, full->phys_addr, prot, mmu_idx);
case ICPR:
return s->pending;
default:
- printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
+ printf("%s: Bad register offset 0x" HWADDR_FMT_plx "\n",
__func__, offset);
return 0;
}
s->int_idle = (value & 1) ? 0 : ~0;
break;
default:
- printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
+ printf("%s: Bad register offset 0x" HWADDR_FMT_plx "\n",
__func__, offset);
break;
}
((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /
(1000 * ((s->rttr & 0xffff) + 1));
default:
- printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
+ printf("%s: Bad register 0x" HWADDR_FMT_plx "\n", __func__, addr);
return 0;
}
}
break;
default:
- printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
+ printf("%s: Bad register 0x" HWADDR_FMT_plx "\n", __func__, addr);
}
}
return s->status;
default:
- printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
+ printf("%s: Bad offset 0x" HWADDR_FMT_plx "\n", __func__, offset);
}
return 0;
break;
default:
- printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
+ printf("%s: Bad offset 0x" HWADDR_FMT_plx "\n", __func__, offset);
}
}
return s->ppfr | ~0x7f001;
default:
- printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
+ printf("%s: Bad offset 0x" HWADDR_FMT_plx "\n", __func__, offset);
}
return 0;
break;
default:
- printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
+ printf("%s: Bad offset 0x" HWADDR_FMT_plx "\n", __func__, offset);
}
}
return s->utsr1;
default:
- printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
+ printf("%s: Bad register 0x" HWADDR_FMT_plx "\n", __func__, addr);
return 0;
}
}
break;
default:
- printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
+ printf("%s: Bad register 0x" HWADDR_FMT_plx "\n", __func__, addr);
}
}
strongarm_ssp_fifo_update(s);
return retval;
default:
- printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
+ printf("%s: Bad register 0x" HWADDR_FMT_plx "\n", __func__, addr);
break;
}
return 0;
break;
default:
- printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
+ printf("%s: Bad register 0x" HWADDR_FMT_plx "\n", __func__, addr);
break;
}
}
error_flash:
qemu_log_mask(LOG_UNIMP, "%s: Unimplemented flash cmd sequence "
- "(offset " TARGET_FMT_plx ", wcycle 0x%x cmd 0x%x value 0x%x)"
+ "(offset " HWADDR_FMT_plx ", wcycle 0x%x cmd 0x%x value 0x%x)"
"\n", __func__, offset, pfl->wcycle, pfl->cmd, value);
mode_read_array:
default:
qemu_log_mask(LOG_UNIMP,
"digic-uart: read access to unknown register 0x"
- TARGET_FMT_plx "\n", addr << 2);
+ HWADDR_FMT_plx "\n", addr << 2);
}
return ret;
default:
qemu_log_mask(LOG_UNIMP,
"digic-uart: write access to unknown register 0x"
- TARGET_FMT_plx "\n", addr << 2);
+ HWADDR_FMT_plx "\n", addr << 2);
}
}
break;
default:
r = s->regs[addr];
- D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, r));
+ D(qemu_log("%s " HWADDR_FMT_plx "=%x\n", __func__, addr, r));
break;
}
return r;
uint32_t value = val64;
unsigned char ch = val64;
- D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, value));
+ D(qemu_log("%s " HWADDR_FMT_plx "=%x\n", __func__, addr, value));
addr >>= 2;
switch (addr)
{
rom->mr = mr;
snprintf(devpath, sizeof(devpath), "/rom@%s", file);
} else {
- snprintf(devpath, sizeof(devpath), "/rom@" TARGET_FMT_plx, addr);
+ snprintf(devpath, sizeof(devpath), "/rom@" HWADDR_FMT_plx, addr);
}
}
"\nThe following two regions overlap (in the %s address space):\n",
rom_as_name(rom));
error_printf(
- " %s (addresses 0x" TARGET_FMT_plx " - 0x" TARGET_FMT_plx ")\n",
+ " %s (addresses 0x" HWADDR_FMT_plx " - 0x" HWADDR_FMT_plx ")\n",
last_rom->name, last_rom->addr, last_rom->addr + last_rom->romsize);
error_printf(
- " %s (addresses 0x" TARGET_FMT_plx " - 0x" TARGET_FMT_plx ")\n",
+ " %s (addresses 0x" HWADDR_FMT_plx " - 0x" HWADDR_FMT_plx ")\n",
rom->name, rom->addr, rom->addr + rom->romsize);
}
rom->romsize,
rom->name);
} else if (!rom->fw_file) {
- g_string_append_printf(buf, "addr=" TARGET_FMT_plx
+ g_string_append_printf(buf, "addr=" HWADDR_FMT_plx
" size=0x%06zx mem=%s name=\"%s\"\n",
rom->addr, rom->romsize,
rom->isrom ? "rom" : "ram",
for (i = 0; i < s->num_mmio; i++) {
size = memory_region_size(s->mmio[i].memory);
- monitor_printf(mon, "%*smmio " TARGET_FMT_plx "/" TARGET_FMT_plx "\n",
+ monitor_printf(mon, "%*smmio " HWADDR_FMT_plx "/" HWADDR_FMT_plx "\n",
indent, "", s->mmio[i].addr, size);
}
}
}
}
if (s->num_mmio) {
- return g_strdup_printf("%s@" TARGET_FMT_plx, qdev_fw_name(dev),
+ return g_strdup_printf("%s@" HWADDR_FMT_plx, qdev_fw_name(dev),
s->mmio[0].addr);
}
if (s->num_pio) {
} else {
val = 0xff;
qemu_log_mask(LOG_GUEST_ERROR,
- "cirrus: mem_readb 0x" TARGET_FMT_plx "\n", addr);
+ "cirrus: mem_readb 0x" HWADDR_FMT_plx "\n", addr);
}
return val;
}
}
} else {
qemu_log_mask(LOG_GUEST_ERROR,
- "cirrus: mem_writeb 0x" TARGET_FMT_plx " "
+ "cirrus: mem_writeb 0x" HWADDR_FMT_plx " "
"value 0x%02" PRIx64 "\n", addr, mem_value);
}
}
break;
default:
{
- error_report("g364: invalid read at [" TARGET_FMT_plx "]",
+ error_report("g364: invalid read at [" HWADDR_FMT_plx "]",
addr);
val = 0;
break;
break;
default:
error_report("g364: invalid write of 0x%" PRIx64
- " at [" TARGET_FMT_plx "]", val, addr);
+ " at [" HWADDR_FMT_plx "]", val, addr);
break;
}
}
uint32_t write_mask, bit_mask, set_mask;
#ifdef DEBUG_VGA_MEM
- printf("vga: [0x" TARGET_FMT_plx "] = 0x%02x\n", addr, val);
+ printf("vga: [0x" HWADDR_FMT_plx "] = 0x%02x\n", addr, val);
#endif
/* convert to VGA memory offset */
memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;
assert(addr < s->vram_size);
s->vram_ptr[addr] = val;
#ifdef DEBUG_VGA_MEM
- printf("vga: chain4: [0x" TARGET_FMT_plx "]\n", addr);
+ printf("vga: chain4: [0x" HWADDR_FMT_plx "]\n", addr);
#endif
s->plane_updated |= mask; /* only used to detect font change */
memory_region_set_dirty(&s->vram, addr, 1);
}
s->vram_ptr[addr] = val;
#ifdef DEBUG_VGA_MEM
- printf("vga: odd/even: [0x" TARGET_FMT_plx "]\n", addr);
+ printf("vga: odd/even: [0x" HWADDR_FMT_plx "]\n", addr);
#endif
s->plane_updated |= mask; /* only used to detect font change */
memory_region_set_dirty(&s->vram, addr, 1);
(((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
(val & write_mask);
#ifdef DEBUG_VGA_MEM
- printf("vga: latch: [0x" TARGET_FMT_plx "] mask=0x%08x val=0x%08x\n",
+ printf("vga: latch: [0x" HWADDR_FMT_plx "] mask=0x%08x val=0x%08x\n",
addr * 4, write_mask, val);
#endif
memory_region_set_dirty(&s->vram, addr << 2, sizeof(uint32_t));
static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
{
- hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA);
+ hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA);
- /* Load and decode. FIXME: handle endianness. */
- D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
+ /* Load and decode. FIXME: handle endianness. */
+ D(printf("%s ch=%d addr=" HWADDR_FMT_plx "\n", __func__, c, addr));
cpu_physical_memory_read(addr, &ctrl->channels[c].current_d,
sizeof(ctrl->channels[c].current_d));
- D(dump_d(c, &ctrl->channels[c].current_d));
- ctrl->channels[c].regs[RW_DATA] = addr;
+ D(dump_d(c, &ctrl->channels[c].current_d));
+ ctrl->channels[c].regs[RW_DATA] = addr;
}
static void channel_store_c(struct fs_dma_ctrl *ctrl, int c)
{
- hwaddr addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
+ hwaddr addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
- /* Encode and store. FIXME: handle endianness. */
- D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
- D(dump_d(c, &ctrl->channels[c].current_d));
+ /* Encode and store. FIXME: handle endianness. */
+ D(printf("%s ch=%d addr=" HWADDR_FMT_plx "\n", __func__, c, addr));
+ D(dump_d(c, &ctrl->channels[c].current_d));
cpu_physical_memory_write(addr, &ctrl->channels[c].current_c,
sizeof(ctrl->channels[c].current_c));
}
static void channel_store_d(struct fs_dma_ctrl *ctrl, int c)
{
- hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA);
+ hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA);
- /* Encode and store. FIXME: handle endianness. */
- D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
+ /* Encode and store. FIXME: handle endianness. */
+ D(printf("%s ch=%d addr=" HWADDR_FMT_plx "\n", __func__, c, addr));
cpu_physical_memory_write(addr, &ctrl->channels[c].current_d,
sizeof(ctrl->channels[c].current_d));
}
static uint32_t dma_rinvalid (void *opaque, hwaddr addr)
{
- hw_error("Unsupported short raccess. reg=" TARGET_FMT_plx "\n", addr);
- return 0;
+ hw_error("Unsupported short raccess. reg=" HWADDR_FMT_plx "\n", addr);
+ return 0;
}
static uint64_t
default:
r = ctrl->channels[c].regs[addr];
- D(printf ("%s c=%d addr=" TARGET_FMT_plx "\n",
+ D(printf("%s c=%d addr=" HWADDR_FMT_plx "\n",
__func__, c, addr));
break;
}
static void
dma_winvalid (void *opaque, hwaddr addr, uint32_t value)
{
- hw_error("Unsupported short waccess. reg=" TARGET_FMT_plx "\n", addr);
+ hw_error("Unsupported short waccess. reg=" HWADDR_FMT_plx "\n", addr);
}
static void
break;
default:
- D(printf ("%s c=%d " TARGET_FMT_plx "\n",
+ D(printf("%s c=%d " HWADDR_FMT_plx "\n",
__func__, c, addr));
break;
}
pl330_exec(s);
} else {
qemu_log_mask(LOG_GUEST_ERROR, "pl330: write of illegal value %u "
- "for offset " TARGET_FMT_plx "\n", (unsigned)value,
+ "for offset " HWADDR_FMT_plx "\n", (unsigned)value,
offset);
}
break;
s->dbg[1] = value;
break;
default:
- qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad write offset " TARGET_FMT_plx
+ qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad write offset " HWADDR_FMT_plx
"\n", offset);
break;
}
chan_id = offset >> 5;
if (chan_id >= s->num_chnls) {
qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
- TARGET_FMT_plx "\n", offset);
+ HWADDR_FMT_plx "\n", offset);
return 0;
}
switch (offset & 0x1f) {
return s->chan[chan_id].lc[1];
default:
qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
- TARGET_FMT_plx "\n", offset);
+ HWADDR_FMT_plx "\n", offset);
return 0;
}
}
chan_id = offset >> 3;
if (chan_id >= s->num_chnls) {
qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
- TARGET_FMT_plx "\n", offset);
+ HWADDR_FMT_plx "\n", offset);
return 0;
}
switch ((offset >> 2) & 1) {
chan_id = offset >> 2;
if (chan_id >= s->num_chnls) {
qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
- TARGET_FMT_plx "\n", offset);
+ HWADDR_FMT_plx "\n", offset);
return 0;
}
return s->chan[chan_id].fault_type;
return s->debug_status;
default:
qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset "
- TARGET_FMT_plx "\n", offset);
+ HWADDR_FMT_plx "\n", offset);
}
return 0;
}
break;
default:
r = s->regs[addr];
- D(qemu_log("%s ch=%d addr=" TARGET_FMT_plx " v=%x\n",
+ D(qemu_log("%s ch=%d addr=" HWADDR_FMT_plx " v=%x\n",
__func__, sid, addr * 4, r));
break;
}
}
break;
default:
- D(qemu_log("%s: ch=%d addr=" TARGET_FMT_plx " v=%x\n",
+ D(qemu_log("%s: ch=%d addr=" HWADDR_FMT_plx " v=%x\n",
__func__, sid, addr * 4, (unsigned)value));
s->regs[addr] = value;
break;
if (result == MEMTX_OK) {
xlnx_csu_dma_data_process(s, buf, len);
} else {
- qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address " TARGET_FMT_plx
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address " HWADDR_FMT_plx
" for mem read", __func__, addr);
s->regs[R_INT_STATUS] |= R_INT_STATUS_AXI_BRESP_ERR_MASK;
xlnx_csu_dma_update_irq(s);
}
if (result != MEMTX_OK) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address " TARGET_FMT_plx
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address " HWADDR_FMT_plx
" for mem write", __func__, addr);
s->regs[R_INT_STATUS] |= R_INT_STATUS_AXI_BRESP_ERR_MASK;
xlnx_csu_dma_update_irq(s);
break;
}
- DPRINTF("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__,
+ DPRINTF("%s: addr " HWADDR_FMT_plx " %02" PRIx32 "\n", __func__,
addr, value);
return (uint64_t)value;
}
{
MPCI2CState *s = opaque;
- DPRINTF("%s: addr " TARGET_FMT_plx " val %08" PRIx64 "\n", __func__,
+ DPRINTF("%s: addr " HWADDR_FMT_plx " val %08" PRIx64 "\n", __func__,
addr, value);
switch (addr) {
case MPC_I2C_ADR:
stl_p(p + MB_MOD_END, end);
stl_p(p + MB_MOD_CMDLINE, cmdline_phys);
- mb_debug("mod%02d: "TARGET_FMT_plx" - "TARGET_FMT_plx,
+ mb_debug("mod%02d: "HWADDR_FMT_plx" - "HWADDR_FMT_plx,
s->mb_mods_count, start, end);
s->mb_mods_count++;
mb_add_mod(&mbs, mbs.mb_buf_phys + offs,
mbs.mb_buf_phys + offs + mb_mod_length, c);
- mb_debug("mod_start: %p\nmod_end: %p\n cmdline: "TARGET_FMT_plx,
+ mb_debug("mod_start: %p\nmod_end: %p\n cmdline: "HWADDR_FMT_plx,
(char *)mbs.mb_buf + offs,
(char *)mbs.mb_buf + offs + mb_mod_length, c);
g_free(one_file);
stl_p(bootinfo + MBI_MMAP_ADDR, ADDR_E820_MAP);
mb_debug("multiboot: entry_addr = %#x", mh_entry_addr);
- mb_debug(" mb_buf_phys = "TARGET_FMT_plx, mbs.mb_buf_phys);
- mb_debug(" mod_start = "TARGET_FMT_plx,
+ mb_debug(" mb_buf_phys = "HWADDR_FMT_plx, mbs.mb_buf_phys);
+ mb_debug(" mod_start = "HWADDR_FMT_plx,
mbs.mb_buf_phys + mbs.offset_mods);
mb_debug(" mb_mods_count = %d", mbs.mb_mods_count);
if (xen_set_mem_type(xen_domid, mem_type,
start_addr >> TARGET_PAGE_BITS,
size >> TARGET_PAGE_BITS)) {
- DPRINTF("xen_set_mem_type error, addr: "TARGET_FMT_plx"\n",
+ DPRINTF("xen_set_mem_type error, addr: "HWADDR_FMT_plx"\n",
start_addr);
}
}
} else {
if (xen_remove_from_physmap(state, start_addr, size) < 0) {
- DPRINTF("physmapping does not exist at "TARGET_FMT_plx"\n", start_addr);
+ DPRINTF("physmapping does not exist at "HWADDR_FMT_plx"\n", start_addr);
}
}
}
#endif
if (errno == ENODATA) {
memory_region_set_dirty(framebuffer, 0, size);
- DPRINTF("xen: track_dirty_vram failed (0x" TARGET_FMT_plx
- ", 0x" TARGET_FMT_plx "): %s\n",
+ DPRINTF("xen: track_dirty_vram failed (0x" HWADDR_FMT_plx
+ ", 0x" HWADDR_FMT_plx "): %s\n",
start_addr, start_addr + size, strerror(errno));
}
return;
entry->lock++;
if (entry->lock == 0) {
fprintf(stderr,
- "mapcache entry lock overflow: "TARGET_FMT_plx" -> %p\n",
+ "mapcache entry lock overflow: "HWADDR_FMT_plx" -> %p\n",
entry->paddr_index, entry->vaddr_base);
abort();
}
if (!found) {
fprintf(stderr, "%s, could not find %p\n", __func__, ptr);
QTAILQ_FOREACH(reventry, &mapcache->locked_entries, next) {
- DPRINTF(" "TARGET_FMT_plx" -> %p is present\n", reventry->paddr_index,
+ DPRINTF(" "HWADDR_FMT_plx" -> %p is present\n", reventry->paddr_index,
reventry->vaddr_req);
}
abort();
if (!found) {
DPRINTF("%s, could not find %p\n", __func__, buffer);
QTAILQ_FOREACH(reventry, &mapcache->locked_entries, next) {
- DPRINTF(" "TARGET_FMT_plx" -> %p is present\n", reventry->paddr_index, reventry->vaddr_req);
+ DPRINTF(" "HWADDR_FMT_plx" -> %p is present\n", reventry->paddr_index, reventry->vaddr_req);
}
return;
}
continue;
}
fprintf(stderr, "Locked DMA mapping while invalidating mapcache!"
- " "TARGET_FMT_plx" -> %p is present\n",
+ " "HWADDR_FMT_plx" -> %p is present\n",
reventry->paddr_index, reventry->vaddr_req);
}
entry = entry->next;
}
if (!entry) {
- DPRINTF("Trying to update an entry for "TARGET_FMT_plx \
+ DPRINTF("Trying to update an entry for "HWADDR_FMT_plx \
"that is not in the mapcache!\n", old_phys_addr);
return NULL;
}
address_index = new_phys_addr >> MCACHE_BUCKET_SHIFT;
address_offset = new_phys_addr & (MCACHE_BUCKET_SIZE - 1);
- fprintf(stderr, "Replacing a dummy mapcache entry for "TARGET_FMT_plx \
- " with "TARGET_FMT_plx"\n", old_phys_addr, new_phys_addr);
+ fprintf(stderr, "Replacing a dummy mapcache entry for "HWADDR_FMT_plx \
+ " with "HWADDR_FMT_plx"\n", old_phys_addr, new_phys_addr);
xen_remap_bucket(entry, entry->vaddr_base,
cache_size, address_index, false);
if (!test_bits(address_offset >> XC_PAGE_SHIFT,
test_bit_size >> XC_PAGE_SHIFT,
entry->valid_mapping)) {
- DPRINTF("Unable to update a mapcache entry for "TARGET_FMT_plx"!\n",
+ DPRINTF("Unable to update a mapcache entry for "HWADDR_FMT_plx"!\n",
old_phys_addr);
return NULL;
}
unsigned size)
{
DPRINTF("Warning: attempted read from physical address "
- "0x" TARGET_FMT_plx " in xen platform mmio space\n", addr);
+ "0x" HWADDR_FMT_plx " in xen platform mmio space\n", addr);
return 0;
}
uint64_t val, unsigned size)
{
DPRINTF("Warning: attempted write of 0x%"PRIx64" to physical "
- "address 0x" TARGET_FMT_plx " in xen platform mmio space\n",
+ "address 0x" HWADDR_FMT_plx " in xen platform mmio space\n",
val, addr);
}
/* WO registers, return unknown value */
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid guest read from WO register at offset "
- TARGET_FMT_plx "\n", __func__, offset);
+ HWADDR_FMT_plx "\n", __func__, offset);
*data = 0;
return true;
default:
/* RO registers, ignore the write */
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid guest write to RO register at offset "
- TARGET_FMT_plx "\n", __func__, offset);
+ HWADDR_FMT_plx "\n", __func__, offset);
return true;
default:
return false;
if (!r) {
qemu_log_mask(LOG_GUEST_ERROR,
- "%s: invalid guest read at offset " TARGET_FMT_plx
+ "%s: invalid guest read at offset " HWADDR_FMT_plx
" size %u\n", __func__, offset, size);
trace_gicv3_dist_badread(offset, size, attrs.secure);
/* The spec requires that reserved registers are RAZ/WI;
if (!r) {
qemu_log_mask(LOG_GUEST_ERROR,
- "%s: invalid guest write at offset " TARGET_FMT_plx
+ "%s: invalid guest write at offset " HWADDR_FMT_plx
" size %u\n", __func__, offset, size);
trace_gicv3_dist_badwrite(offset, data, size, attrs.secure);
/* The spec requires that reserved registers are RAZ/WI;
/* RO register, ignore the write */
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid guest write to RO register at offset "
- TARGET_FMT_plx "\n", __func__, offset);
+ HWADDR_FMT_plx "\n", __func__, offset);
}
break;
case GITS_CREADR + 4:
/* RO register, ignore the write */
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid guest write to RO register at offset "
- TARGET_FMT_plx "\n", __func__, offset);
+ HWADDR_FMT_plx "\n", __func__, offset);
}
break;
case GITS_BASER ... GITS_BASER + 0x3f:
/* RO registers, ignore the write */
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid guest write to RO register at offset "
- TARGET_FMT_plx "\n", __func__, offset);
+ HWADDR_FMT_plx "\n", __func__, offset);
break;
default:
result = false;
/* RO register, ignore the write */
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid guest write to RO register at offset "
- TARGET_FMT_plx "\n", __func__, offset);
+ HWADDR_FMT_plx "\n", __func__, offset);
}
break;
case GITS_TYPER:
/* RO registers, ignore the write */
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid guest write to RO register at offset "
- TARGET_FMT_plx "\n", __func__, offset);
+ HWADDR_FMT_plx "\n", __func__, offset);
break;
default:
result = false;
if (!result) {
qemu_log_mask(LOG_GUEST_ERROR,
- "%s: invalid guest read at offset " TARGET_FMT_plx
+ "%s: invalid guest read at offset " HWADDR_FMT_plx
" size %u\n", __func__, offset, size);
trace_gicv3_its_badread(offset, size);
/*
if (!result) {
qemu_log_mask(LOG_GUEST_ERROR,
- "%s: invalid guest write at offset " TARGET_FMT_plx
+ "%s: invalid guest write at offset " HWADDR_FMT_plx
" size %u\n", __func__, offset, size);
trace_gicv3_its_badwrite(offset, data, size);
/*
/* RO registers, ignore the write */
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid guest write to RO register at offset "
- TARGET_FMT_plx "\n", __func__, offset);
+ HWADDR_FMT_plx "\n", __func__, offset);
return MEMTX_OK;
/*
* VLPI frame registers. We don't need a version check for
/* RO register, ignore the write */
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid guest write to RO register at offset "
- TARGET_FMT_plx "\n", __func__, offset);
+ HWADDR_FMT_plx "\n", __func__, offset);
return MEMTX_OK;
/*
* VLPI frame registers. We don't need a version check for
if (r != MEMTX_OK) {
qemu_log_mask(LOG_GUEST_ERROR,
- "%s: invalid guest read at offset " TARGET_FMT_plx
+ "%s: invalid guest read at offset " HWADDR_FMT_plx
" size %u\n", __func__, offset, size);
trace_gicv3_redist_badread(gicv3_redist_affid(cs), offset,
size, attrs.secure);
if (r != MEMTX_OK) {
qemu_log_mask(LOG_GUEST_ERROR,
- "%s: invalid guest write at offset " TARGET_FMT_plx
+ "%s: invalid guest write at offset " HWADDR_FMT_plx
" size %u\n", __func__, offset, size);
trace_gicv3_redist_badwrite(gicv3_redist_affid(cs), offset, data,
size, attrs.secure);
default:
if (offset >> 2 >= IIC_REGSET_SIZE) {
hw_error("exynos4210.combiner: overflow of reg_set by 0x"
- TARGET_FMT_plx "offset\n", offset);
+ HWADDR_FMT_plx "offset\n", offset);
}
val = s->reg_set[offset >> 2];
}
if (req_quad_base_n >= IIC_NGRP) {
hw_error("exynos4210.combiner: unallowed write access at offset 0x"
- TARGET_FMT_plx "\n", offset);
+ HWADDR_FMT_plx "\n", offset);
return;
}
if (reg_n > 1) {
hw_error("exynos4210.combiner: unallowed write access at offset 0x"
- TARGET_FMT_plx "\n", offset);
+ HWADDR_FMT_plx "\n", offset);
return;
}
if (offset >> 2 >= IIC_REGSET_SIZE) {
hw_error("exynos4210.combiner: overflow of reg_set by 0x"
- TARGET_FMT_plx "offset\n", offset);
+ HWADDR_FMT_plx "offset\n", offset);
}
s->reg_set[offset >> 2] = val;
break;
default:
hw_error("exynos4210.combiner: unallowed write access at offset 0x"
- TARGET_FMT_plx "\n", offset);
+ HWADDR_FMT_plx "\n", offset);
break;
}
}
s = AUX_SLAVE(dev);
- monitor_printf(mon, "%*smemory " TARGET_FMT_plx "/" TARGET_FMT_plx "\n",
+ monitor_printf(mon, "%*smemory " HWADDR_FMT_plx "/" HWADDR_FMT_plx "\n",
indent, "",
object_property_get_uint(OBJECT(s->mmio), "addr", NULL),
memory_region_size(s->mmio));
addr &= 0xfc;
- IVSHMEM_DPRINTF("writing to addr " TARGET_FMT_plx "\n", addr);
+ IVSHMEM_DPRINTF("writing to addr " HWADDR_FMT_plx "\n", addr);
switch (addr)
{
case INTRMASK:
}
break;
default:
- IVSHMEM_DPRINTF("Unhandled write " TARGET_FMT_plx "\n", addr);
+ IVSHMEM_DPRINTF("Unhandled write " HWADDR_FMT_plx "\n", addr);
}
}
break;
default:
- IVSHMEM_DPRINTF("why are we reading " TARGET_FMT_plx "\n", addr);
+ IVSHMEM_DPRINTF("why are we reading " HWADDR_FMT_plx "\n", addr);
ret = 0;
}
DBDMA_channel *ch = &s->channels[channel];
int reg = (addr - (channel << DBDMA_CHANNEL_SHIFT)) >> 2;
- DBDMA_DPRINTFCH(ch, "writel 0x" TARGET_FMT_plx " <= 0x%08"PRIx64"\n",
+ DBDMA_DPRINTFCH(ch, "writel 0x" HWADDR_FMT_plx " <= 0x%08"PRIx64"\n",
addr, value);
DBDMA_DPRINTFCH(ch, "channel 0x%x reg 0x%x\n",
(uint32_t)addr >> DBDMA_CHANNEL_SHIFT, reg);
break;
}
- DBDMA_DPRINTFCH(ch, "readl 0x" TARGET_FMT_plx " => 0x%08x\n", addr, value);
+ DBDMA_DPRINTFCH(ch, "readl 0x" HWADDR_FMT_plx " => 0x%08x\n", addr, value);
DBDMA_DPRINTFCH(ch, "channel 0x%x reg 0x%x\n",
(uint32_t)addr >> DBDMA_CHANNEL_SHIFT, reg);
return s->pcmcia1;
default:
printf("Mainstone - mst_fpga_readb: Bad register offset "
- "0x" TARGET_FMT_plx "\n", addr);
+ "0x" HWADDR_FMT_plx "\n", addr);
}
return 0;
}
break;
default:
printf("Mainstone - mst_fpga_writeb: Bad register offset "
- "0x" TARGET_FMT_plx "\n", addr);
+ "0x" HWADDR_FMT_plx "\n", addr);
}
}
break;
default:
qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to unknown "
- "EMAC register 0x" TARGET_FMT_plx "\n",
+ "EMAC register 0x" HWADDR_FMT_plx "\n",
offset);
}
break;
default:
qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to unknown "
- "EMAC register 0x" TARGET_FMT_plx "\n",
+ "EMAC register 0x" HWADDR_FMT_plx "\n",
offset);
}
}
default:
qemu_log_mask(LOG_UNIMP,
"allwinner_emac: read access to unknown register 0x"
- TARGET_FMT_plx "\n", offset);
+ HWADDR_FMT_plx "\n", offset);
ret = 0;
}
default:
qemu_log_mask(LOG_UNIMP,
"allwinner_emac: write access to unknown register 0x"
- TARGET_FMT_plx "\n", offset);
+ HWADDR_FMT_plx "\n", offset);
}
}
break;
}
- DPRINTF("Read 0x%08x @ 0x" TARGET_FMT_plx
+ DPRINTF("Read 0x%08x @ 0x" HWADDR_FMT_plx
" : %s (%s)\n",
ret, addr, reg->name, reg->desc);
}
}
- DPRINTF("Write 0x%08x @ 0x" TARGET_FMT_plx
+ DPRINTF("Write 0x%08x @ 0x" HWADDR_FMT_plx
" val:0x%08x->0x%08x : %s (%s)\n",
(unsigned int)value, addr, before, reg->value,
reg->name, reg->desc);
{
assert(bd != NULL);
- RING_DEBUG("READ Buffer Descriptor @ 0x" TARGET_FMT_plx"\n", addr);
+ RING_DEBUG("READ Buffer Descriptor @ 0x" HWADDR_FMT_plx"\n", addr);
cpu_physical_memory_read(addr,
bd,
sizeof(eTSEC_rxtx_bd));
stl_be_p(&bd->bufptr, bd->bufptr);
}
- RING_DEBUG("Write Buffer Descriptor @ 0x" TARGET_FMT_plx"\n", addr);
+ RING_DEBUG("Write Buffer Descriptor @ 0x" HWADDR_FMT_plx"\n", addr);
cpu_physical_memory_write(addr,
bd,
sizeof(eTSEC_rxtx_bd));
s->csr[37] = nnrd >> 16;
#ifdef PCNET_DEBUG
if (bad) {
- printf("pcnet: BAD RMD RECORDS AFTER 0x" TARGET_FMT_plx "\n",
+ printf("pcnet: BAD RMD RECORDS AFTER 0x" HWADDR_FMT_plx "\n",
crda);
}
} else {
- printf("pcnet: BAD RMD RDA=0x" TARGET_FMT_plx "\n", crda);
+ printf("pcnet: BAD RMD RDA=0x" HWADDR_FMT_plx "\n", crda);
#endif
}
}
}
break;
default:
- DPRINTF("not implemented dma reg write(l) addr=0x" TARGET_FMT_plx
+ DPRINTF("not implemented dma reg write(l) addr=0x" HWADDR_FMT_plx
" val=0x%08x (ring %d, addr=0x%02x)\n",
addr, val, index, offset);
break;
r->lower32 = 0;
break;
default:
- DPRINTF("not implemented write(l) addr=0x" TARGET_FMT_plx
+ DPRINTF("not implemented write(l) addr=0x" HWADDR_FMT_plx
" val=0x%08x\n", addr, val);
break;
}
desc_ring_set_base_addr(r->rings[index], val);
break;
default:
- DPRINTF("not implemented dma reg write(q) addr=0x" TARGET_FMT_plx
- " val=0x" TARGET_FMT_plx " (ring %d, offset=0x%02x)\n",
+ DPRINTF("not implemented dma reg write(q) addr=0x" HWADDR_FMT_plx
+ " val=0x" HWADDR_FMT_plx " (ring %d, offset=0x%02x)\n",
addr, val, index, offset);
break;
}
rocker_port_phys_enable_write(r, val);
break;
default:
- DPRINTF("not implemented write(q) addr=0x" TARGET_FMT_plx
- " val=0x" TARGET_FMT_plx "\n", addr, val);
+ DPRINTF("not implemented write(q) addr=0x" HWADDR_FMT_plx
+ " val=0x" HWADDR_FMT_plx "\n", addr, val);
break;
}
}
static void rocker_mmio_write(void *opaque, hwaddr addr, uint64_t val,
unsigned size)
{
- DPRINTF("Write %s addr " TARGET_FMT_plx
- ", size %u, val " TARGET_FMT_plx "\n",
+ DPRINTF("Write %s addr " HWADDR_FMT_plx
+ ", size %u, val " HWADDR_FMT_plx "\n",
rocker_reg_name(opaque, addr), addr, size, val);
switch (size) {
ret = desc_ring_get_credits(r->rings[index]);
break;
default:
- DPRINTF("not implemented dma reg read(l) addr=0x" TARGET_FMT_plx
+ DPRINTF("not implemented dma reg read(l) addr=0x" HWADDR_FMT_plx
" (ring %d, addr=0x%02x)\n", addr, index, offset);
ret = 0;
break;
ret = (uint32_t)(r->switch_id >> 32);
break;
default:
- DPRINTF("not implemented read(l) addr=0x" TARGET_FMT_plx "\n", addr);
+ DPRINTF("not implemented read(l) addr=0x" HWADDR_FMT_plx "\n", addr);
ret = 0;
break;
}
ret = desc_ring_get_base_addr(r->rings[index]);
break;
default:
- DPRINTF("not implemented dma reg read(q) addr=0x" TARGET_FMT_plx
+ DPRINTF("not implemented dma reg read(q) addr=0x" HWADDR_FMT_plx
" (ring %d, addr=0x%02x)\n", addr, index, offset);
ret = 0;
break;
ret = r->switch_id;
break;
default:
- DPRINTF("not implemented read(q) addr=0x" TARGET_FMT_plx "\n", addr);
+ DPRINTF("not implemented read(q) addr=0x" HWADDR_FMT_plx "\n", addr);
ret = 0;
break;
}
static uint64_t rocker_mmio_read(void *opaque, hwaddr addr, unsigned size)
{
- DPRINTF("Read %s addr " TARGET_FMT_plx ", size %u\n",
+ DPRINTF("Read %s addr " HWADDR_FMT_plx ", size %u\n",
rocker_reg_name(opaque, addr), addr, size);
switch (size) {
bool desc_ring_set_base_addr(DescRing *ring, uint64_t base_addr)
{
if (base_addr & 0x7) {
- DPRINTF("ERROR: ring[%d] desc base addr (0x" TARGET_FMT_plx
+ DPRINTF("ERROR: ring[%d] desc base addr (0x" HWADDR_FMT_plx
") not 8-byte aligned\n", ring->index, base_addr);
return false;
}
if (addr < ARRAY_SIZE(s->regs)) {
r = s->regs[addr];
}
- DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n",
+ DENET(qemu_log("%s addr=" HWADDR_FMT_plx " v=%x\n",
__func__, addr * 4, r));
break;
}
break;
default:
- DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n",
+ DENET(qemu_log("%s addr=" HWADDR_FMT_plx " v=%x\n",
__func__, addr * 4, (unsigned)value));
if (addr < ARRAY_SIZE(s->regs)) {
s->regs[addr] = value;
case R_RX_CTRL1:
case R_RX_CTRL0:
r = s->regs[addr];
- D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr * 4, r));
+ D(qemu_log("%s " HWADDR_FMT_plx "=%x\n", __func__, addr * 4, r));
break;
default:
if (addr == R_TX_CTRL1)
base = 0x800 / 4;
- D(qemu_log("%s addr=" TARGET_FMT_plx " val=%x\n",
+ D(qemu_log("%s addr=" HWADDR_FMT_plx " val=%x\n",
__func__, addr * 4, value));
if ((value & (CTRL_P | CTRL_S)) == CTRL_S) {
qemu_send_packet(qemu_get_queue(s->nic),
case R_TX_LEN0:
case R_TX_LEN1:
case R_TX_GIE0:
- D(qemu_log("%s addr=" TARGET_FMT_plx " val=%x\n",
+ D(qemu_log("%s addr=" HWADDR_FMT_plx " val=%x\n",
__func__, addr * 4, value));
s->regs[addr] = value;
break;
main_host_sbd = SYS_BUS_DEVICE(main_host);
if (main_host_sbd->num_mmio > 0) {
- return g_strdup_printf(TARGET_FMT_plx ",%x",
+ return g_strdup_printf(HWADDR_FMT_plx ",%x",
main_host_sbd->mmio[0].addr, position + 1);
}
if (main_host_sbd->num_pio > 0) {
saddr = addr >> 2;
- DPRINTF("bonito_writel "TARGET_FMT_plx" val %lx saddr %x\n",
+ DPRINTF("bonito_writel "HWADDR_FMT_plx" val %lx saddr %x\n",
addr, val, saddr);
switch (saddr) {
case BONITO_BONPONCFG:
saddr = addr >> 2;
- DPRINTF("bonito_readl "TARGET_FMT_plx"\n", addr);
+ DPRINTF("bonito_readl "HWADDR_FMT_plx"\n", addr);
switch (saddr) {
case BONITO_INTISR:
return s->regs[saddr];
PCIBonitoState *s = opaque;
PCIDevice *d = PCI_DEVICE(s);
- DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %lx\n", addr, val);
+ DPRINTF("bonito_pciconf_writel "HWADDR_FMT_plx" val %lx\n", addr, val);
d->config_write(d, addr, val, 4);
}
PCIBonitoState *s = opaque;
PCIDevice *d = PCI_DEVICE(s);
- DPRINTF("bonito_pciconf_readl "TARGET_FMT_plx"\n", addr);
+ DPRINTF("bonito_pciconf_readl "HWADDR_FMT_plx"\n", addr);
return d->config_read(d, addr, 4);
}
regno = (cfgaddr & BONITO_PCICONF_REG_MASK_HW) >> BONITO_PCICONF_REG_OFFSET;
if (idsel == 0) {
- error_report("error in bonito pci config address 0x" TARGET_FMT_plx
+ error_report("error in bonito pci config address 0x" HWADDR_FMT_plx
",pcimap_cfg=0x%x", addr, s->regs[BONITO_PCIMAP_CFG]);
exit(1);
}
uint32_t pciaddr;
uint16_t status;
- DPRINTF("bonito_spciconf_write "TARGET_FMT_plx" size %d val %lx\n",
+ DPRINTF("bonito_spciconf_write "HWADDR_FMT_plx" size %d val %lx\n",
addr, size, val);
pciaddr = bonito_sbridge_pciaddr(s, addr);
uint32_t pciaddr;
uint16_t status;
- DPRINTF("bonito_spciconf_read "TARGET_FMT_plx" size %d\n", addr, size);
+ DPRINTF("bonito_spciconf_read "HWADDR_FMT_plx" size %d\n", addr, size);
pciaddr = bonito_sbridge_pciaddr(s, addr);
break;
}
- pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__,
+ pci_debug("%s: win:%lx(addr:" HWADDR_FMT_plx ") -> value:%x\n", __func__,
win, addr, value);
return value;
}
win = addr & 0xfe0;
- pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n",
+ pci_debug("%s: value:%x -> win:%lx(addr:" HWADDR_FMT_plx ")\n",
__func__, (unsigned)value, win, addr);
switch (win) {
{
PCIHostState *s = opaque;
- PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx64"\n",
+ PCI_DPRINTF("%s addr " HWADDR_FMT_plx " len %d val %"PRIx64"\n",
__func__, addr, len, val);
if (addr != 0 || len != 4) {
return;
PCIHostState *s = opaque;
uint32_t val = s->config_reg;
- PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx32"\n",
+ PCI_DPRINTF("%s addr " HWADDR_FMT_plx " len %d val %"PRIx32"\n",
__func__, addr, len, val);
return val;
}
bcr = 0x8000;
break;
default:
- error_report("invalid RAM size " TARGET_FMT_plx, ram_size);
+ error_report("invalid RAM size " HWADDR_FMT_plx, ram_size);
return 0;
}
bcr |= ram_base >> 2 & 0xffe00000;
default:
qemu_log_mask(LOG_GUEST_ERROR,
- "exynos4210.rtc: bad read offset " TARGET_FMT_plx,
+ "exynos4210.rtc: bad read offset " HWADDR_FMT_plx,
offset);
break;
}
default:
qemu_log_mask(LOG_GUEST_ERROR,
- "exynos4210.rtc: bad write offset " TARGET_FMT_plx,
+ "exynos4210.rtc: bad write offset " HWADDR_FMT_plx,
offset);
break;
static void error_access(const char *kind, hwaddr addr)
{
- fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") not supported\n",
+ fprintf(stderr, "%s to %s (0x" HWADDR_FMT_plx ") not supported\n",
kind, regname(addr), addr);
}
static void ignore_access(const char *kind, hwaddr addr)
{
- fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") ignored\n",
+ fprintf(stderr, "%s to %s (0x" HWADDR_FMT_plx ") ignored\n",
kind, regname(addr), addr);
}
break;
}
- DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, r);
+ DB_PRINT("addr=" HWADDR_FMT_plx " = %x\n", addr * 4, r);
xlx_spi_update_irq(s);
return r;
}
XilinxSPI *s = opaque;
uint32_t value = val64;
- DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr, value);
+ DB_PRINT("addr=" HWADDR_FMT_plx " = %x\n", addr, value);
addr >>= 2;
switch (addr) {
case R_SRR:
case R_INTR_STATUS:
ret = s->regs[addr] & IXR_ALL;
s->regs[addr] = 0;
- DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
+ DB_PRINT_L(0, "addr=" HWADDR_FMT_plx " = %x\n", addr * 4, ret);
xilinx_spips_update_ixr(s);
return ret;
case R_INTR_MASK:
if (!(s->regs[R_CONFIG] & R_CONFIG_ENDIAN)) {
ret <<= 8 * shortfall;
}
- DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
+ DB_PRINT_L(0, "addr=" HWADDR_FMT_plx " = %x\n", addr * 4, ret);
xilinx_spips_check_flush(s);
xilinx_spips_update_ixr(s);
return ret;
}
- DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4,
+ DB_PRINT_L(0, "addr=" HWADDR_FMT_plx " = %x\n", addr * 4,
s->regs[addr] & mask);
return s->regs[addr] & mask;
XilinxSPIPS *s = opaque;
bool try_flush = true;
- DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value);
+ DB_PRINT_L(0, "addr=" HWADDR_FMT_plx " = %x\n", addr, (unsigned)value);
addr >>= 2;
switch (addr) {
case R_CONFIG:
default:
qemu_log_mask(LOG_UNIMP,
"digic-timer: read access to unknown register 0x"
- TARGET_FMT_plx "\n", offset);
+ HWADDR_FMT_plx "\n", offset);
}
return ret;
default:
qemu_log_mask(LOG_UNIMP,
"digic-timer: read access to unknown register 0x"
- TARGET_FMT_plx "\n", offset);
+ HWADDR_FMT_plx "\n", offset);
}
}
t->rw_ack_intr = 0;
break;
default:
- printf ("%s " TARGET_FMT_plx " %x\n",
- __func__, addr, value);
+ printf("%s " HWADDR_FMT_plx " %x\n", __func__, addr, value);
break;
}
}
case L0_ICNTO: case L1_ICNTO:
case L0_FRCNTO: case L1_FRCNTO:
qemu_log_mask(LOG_GUEST_ERROR,
- "exynos4210.mct: write to RO register " TARGET_FMT_plx,
+ "exynos4210.mct: write to RO register " HWADDR_FMT_plx,
offset);
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
- "exynos4210.pwm: bad read offset " TARGET_FMT_plx,
+ "exynos4210.pwm: bad read offset " HWADDR_FMT_plx,
offset);
break;
}
default:
qemu_log_mask(LOG_GUEST_ERROR,
- "exynos4210.pwm: bad write offset " TARGET_FMT_plx,
+ "exynos4210.pwm: bad write offset " HWADDR_FMT_plx,
offset);
break;
assert(section.mr);
if (proxy_path) {
- path = g_strdup_printf("%s/virtio-mmio@" TARGET_FMT_plx, proxy_path,
+ path = g_strdup_printf("%s/virtio-mmio@" HWADDR_FMT_plx, proxy_path,
section.offset_within_address_space);
} else {
- path = g_strdup_printf("virtio-mmio@" TARGET_FMT_plx,
+ path = g_strdup_printf("virtio-mmio@" HWADDR_FMT_plx,
section.offset_within_address_space);
}
memory_region_unref(section.mr);
PCIDevice *d = o;
/* if this function is called, that probably means that there is a
* misconfiguration of the IOMMU. */
- XEN_PT_ERR(d, "Should not read BAR through QEMU. @0x"TARGET_FMT_plx"\n",
+ XEN_PT_ERR(d, "Should not read BAR through QEMU. @0x"HWADDR_FMT_plx"\n",
addr);
return 0;
}
{
PCIDevice *d = o;
/* Same comment as xen_pt_bar_read function */
- XEN_PT_ERR(d, "Should not write BAR through QEMU. @0x"TARGET_FMT_plx"\n",
+ XEN_PT_ERR(d, "Should not write BAR through QEMU. @0x"HWADDR_FMT_plx"\n",
addr);
}
typedef uint64_t hwaddr;
#define HWADDR_MAX UINT64_MAX
-#define TARGET_FMT_plx "%016" PRIx64
+#define HWADDR_FMT_plx "%016" PRIx64
#define HWADDR_PRId PRId64
#define HWADDR_PRIi PRIi64
#define HWADDR_PRIo PRIo64
while (len > 0) {
if (is_physical) {
- monitor_printf(mon, TARGET_FMT_plx ":", addr);
+ monitor_printf(mon, HWADDR_FMT_plx ":", addr);
} else {
monitor_printf(mon, TARGET_FMT_lx ":", (target_ulong)addr);
}
unsigned size)
{
#ifdef DEBUG_UNASSIGNED
- printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
+ printf("Unassigned mem read " HWADDR_FMT_plx "\n", addr);
#endif
return 0;
}
uint64_t val, unsigned size)
{
#ifdef DEBUG_UNASSIGNED
- printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
+ printf("Unassigned mem write " HWADDR_FMT_plx " = 0x%"PRIx64"\n", addr, val);
#endif
}
for (i = 0; i < level; i++) {
qemu_printf(MTREE_INDENT);
}
- qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx
- " (prio %d, %s%s): alias %s @%s " TARGET_FMT_plx
- "-" TARGET_FMT_plx "%s",
+ qemu_printf(HWADDR_FMT_plx "-" HWADDR_FMT_plx
+ " (prio %d, %s%s): alias %s @%s " HWADDR_FMT_plx
+ "-" HWADDR_FMT_plx "%s",
cur_start, cur_end,
mr->priority,
mr->nonvolatile ? "nv-" : "",
for (i = 0; i < level; i++) {
qemu_printf(MTREE_INDENT);
}
- qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx
+ qemu_printf(HWADDR_FMT_plx "-" HWADDR_FMT_plx
" (prio %d, %s%s): %s%s",
cur_start, cur_end,
mr->priority,
while (n--) {
mr = range->mr;
if (range->offset_in_region) {
- qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx
- " (prio %d, %s%s): %s @" TARGET_FMT_plx,
+ qemu_printf(MTREE_INDENT HWADDR_FMT_plx "-" HWADDR_FMT_plx
+ " (prio %d, %s%s): %s @" HWADDR_FMT_plx,
int128_get64(range->addr.start),
int128_get64(range->addr.start)
+ MR_SIZE(range->addr.size),
memory_region_name(mr),
range->offset_in_region);
} else {
- qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx
+ qemu_printf(MTREE_INDENT HWADDR_FMT_plx "-" HWADDR_FMT_plx
" (prio %d, %s%s): %s",
int128_get64(range->addr.start),
int128_get64(range->addr.start)
}
#ifdef DEBUG_GUEST_PHYS_REGION_ADD
- fprintf(stderr, "%s: target_start=" TARGET_FMT_plx " target_end="
- TARGET_FMT_plx ": %s (count: %u)\n", __func__, target_start,
+ fprintf(stderr, "%s: target_start=" HWADDR_FMT_plx " target_end="
+ HWADDR_FMT_plx ": %s (count: %u)\n", __func__, target_start,
target_end, predecessor ? "joined" : "added", g->list->num);
#endif
}
MemTxResult res;
#if defined(DEBUG_SUBPAGE)
- printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__,
+ printf("%s: subpage %p len %u addr " HWADDR_FMT_plx "\n", __func__,
subpage, len, addr);
#endif
res = flatview_read(subpage->fv, addr + subpage->base, attrs, buf, len);
uint8_t buf[8];
#if defined(DEBUG_SUBPAGE)
- printf("%s: subpage %p len %u addr " TARGET_FMT_plx
+ printf("%s: subpage %p len %u addr " HWADDR_FMT_plx
" value %"PRIx64"\n",
__func__, subpage, len, addr, value);
#endif
{
subpage_t *subpage = opaque;
#if defined(DEBUG_SUBPAGE)
- printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n",
+ printf("%s: subpage %p %c len %u addr " HWADDR_FMT_plx "\n",
__func__, subpage, is_write ? 'w' : 'r', len, addr);
#endif
NULL, TARGET_PAGE_SIZE);
mmio->iomem.subpage = true;
#if defined(DEBUG_SUBPAGE)
- printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__,
+ printf("%s: %p base " HWADDR_FMT_plx " len %08x\n", __func__,
mmio, base, TARGET_PAGE_SIZE);
#endif
const char *names[] = { " [unassigned]", " [not dirty]",
" [ROM]", " [watch]" };
- qemu_printf(" #%d @" TARGET_FMT_plx ".." TARGET_FMT_plx
+ qemu_printf(" #%d @" HWADDR_FMT_plx ".." HWADDR_FMT_plx
" %s%s%s%s%s",
i,
s->offset_within_address_space,
{
addr = addr_canonical(env, addr);
- monitor_printf(mon, TARGET_FMT_plx ": " TARGET_FMT_plx
+ monitor_printf(mon, HWADDR_FMT_plx ": " HWADDR_FMT_plx
" %c%c%c%c%c%c%c%c%c\n",
addr,
pte & mask,
prot1 = *plast_prot;
if (prot != prot1) {
if (*pstart != -1) {
- monitor_printf(mon, TARGET_FMT_plx "-" TARGET_FMT_plx " "
- TARGET_FMT_plx " %c%c%c\n",
+ monitor_printf(mon, HWADDR_FMT_plx "-" HWADDR_FMT_plx " "
+ HWADDR_FMT_plx " %c%c%c\n",
addr_canonical(env, *pstart),
addr_canonical(env, end),
addr_canonical(env, end - *pstart),
physical & TARGET_PAGE_MASK, prot,
mmu_idx, TARGET_PAGE_SIZE);
qemu_log_mask(CPU_LOG_MMU,
- "%s address=%" VADDR_PRIx " physical " TARGET_FMT_plx
+ "%s address=%" VADDR_PRIx " physical " HWADDR_FMT_plx
" prot %d\n", __func__, address, physical, prot);
return true;
} else {
CPUMBState *env = &cpu->env;
qemu_log_mask(CPU_LOG_INT, "Transaction failed: vaddr 0x%" VADDR_PRIx
- " physaddr 0x" TARGET_FMT_plx " size %d access type %s\n",
+ " physaddr 0x" HWADDR_FMT_plx " size %d access type %s\n",
addr, physaddr, size,
access_type == MMU_INST_FETCH ? "INST_FETCH" :
(access_type == MMU_DATA_LOAD ? "DATA_LOAD" : "DATA_STORE"));
switch (ret) {
case TLBRET_MATCH:
qemu_log_mask(CPU_LOG_MMU,
- "%s address=%" VADDR_PRIx " physical " TARGET_FMT_plx
+ "%s address=%" VADDR_PRIx " physical " HWADDR_FMT_plx
" prot %d\n", __func__, address, physical, prot);
break;
default:
ptem = (vsid << 7) | (pgidx >> 10);
/* Page address translation */
- qemu_log_mask(CPU_LOG_MMU, "htab_base " TARGET_FMT_plx
- " htab_mask " TARGET_FMT_plx
- " hash " TARGET_FMT_plx "\n",
+ qemu_log_mask(CPU_LOG_MMU, "htab_base " HWADDR_FMT_plx
+ " htab_mask " HWADDR_FMT_plx
+ " hash " HWADDR_FMT_plx "\n",
ppc_hash32_hpt_base(cpu), ppc_hash32_hpt_mask(cpu), hash);
/* Primary PTEG lookup */
- qemu_log_mask(CPU_LOG_MMU, "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
+ qemu_log_mask(CPU_LOG_MMU, "0 htab=" HWADDR_FMT_plx "/" HWADDR_FMT_plx
" vsid=%" PRIx32 " ptem=%" PRIx32
- " hash=" TARGET_FMT_plx "\n",
+ " hash=" HWADDR_FMT_plx "\n",
ppc_hash32_hpt_base(cpu), ppc_hash32_hpt_mask(cpu),
vsid, ptem, hash);
pteg_off = get_pteg_offset32(cpu, hash);
pte_offset = ppc_hash32_pteg_search(cpu, pteg_off, 0, ptem, pte);
if (pte_offset == -1) {
/* Secondary PTEG lookup */
- qemu_log_mask(CPU_LOG_MMU, "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
+ qemu_log_mask(CPU_LOG_MMU, "1 htab=" HWADDR_FMT_plx "/" HWADDR_FMT_plx
" vsid=%" PRIx32 " api=%" PRIx32
- " hash=" TARGET_FMT_plx "\n", ppc_hash32_hpt_base(cpu),
+ " hash=" HWADDR_FMT_plx "\n", ppc_hash32_hpt_base(cpu),
ppc_hash32_hpt_mask(cpu), vsid, ptem, ~hash);
pteg_off = get_pteg_offset32(cpu, ~hash);
pte_offset = ppc_hash32_pteg_search(cpu, pteg_off, 1, ptem, pte);
/* Page address translation */
qemu_log_mask(CPU_LOG_MMU,
- "htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
- " hash " TARGET_FMT_plx "\n",
+ "htab_base " HWADDR_FMT_plx " htab_mask " HWADDR_FMT_plx
+ " hash " HWADDR_FMT_plx "\n",
ppc_hash64_hpt_base(cpu), ppc_hash64_hpt_mask(cpu), hash);
/* Primary PTEG lookup */
qemu_log_mask(CPU_LOG_MMU,
- "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
+ "0 htab=" HWADDR_FMT_plx "/" HWADDR_FMT_plx
" vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
- " hash=" TARGET_FMT_plx "\n",
+ " hash=" HWADDR_FMT_plx "\n",
ppc_hash64_hpt_base(cpu), ppc_hash64_hpt_mask(cpu),
vsid, ptem, hash);
ptex = ppc_hash64_pteg_search(cpu, hash, sps, ptem, pte, pshift);
/* Secondary PTEG lookup */
ptem |= HPTE64_V_SECONDARY;
qemu_log_mask(CPU_LOG_MMU,
- "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
+ "1 htab=" HWADDR_FMT_plx "/" HWADDR_FMT_plx
" vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
- " hash=" TARGET_FMT_plx "\n", ppc_hash64_hpt_base(cpu),
+ " hash=" HWADDR_FMT_plx "\n", ppc_hash64_hpt_base(cpu),
ppc_hash64_hpt_mask(cpu), vsid, ptem, ~hash);
ptex = ppc_hash64_pteg_search(cpu, ~hash, sps, ptem, pte, pshift);
}
if (best != -1) {
done:
- qemu_log_mask(CPU_LOG_MMU, "found TLB at addr " TARGET_FMT_plx
+ qemu_log_mask(CPU_LOG_MMU, "found TLB at addr " HWADDR_FMT_plx
" prot=%01x ret=%d\n",
ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
/* Update page flags */
ctx->prot = prot;
ret = check_prot(ctx->prot, access_type);
if (ret == 0) {
- qemu_log_mask(CPU_LOG_MMU, "BAT %d match: r " TARGET_FMT_plx
+ qemu_log_mask(CPU_LOG_MMU, "BAT %d match: r " HWADDR_FMT_plx
" prot=%c%c\n", i, ctx->raddr,
ctx->prot & PAGE_READ ? 'R' : '-',
ctx->prot & PAGE_WRITE ? 'W' : '-');
/* Check if instruction fetch is allowed, if needed */
if (type != ACCESS_CODE || ctx->nx == 0) {
/* Page address translation */
- qemu_log_mask(CPU_LOG_MMU, "htab_base " TARGET_FMT_plx
- " htab_mask " TARGET_FMT_plx
- " hash " TARGET_FMT_plx "\n",
+ qemu_log_mask(CPU_LOG_MMU, "htab_base " HWADDR_FMT_plx
+ " htab_mask " HWADDR_FMT_plx
+ " hash " HWADDR_FMT_plx "\n",
ppc_hash32_hpt_base(cpu), ppc_hash32_hpt_mask(cpu), hash);
ctx->hash[0] = hash;
ctx->hash[1] = ~hash;
hwaddr curaddr;
uint32_t a0, a1, a2, a3;
- qemu_log("Page table: " TARGET_FMT_plx " len " TARGET_FMT_plx
+ qemu_log("Page table: " HWADDR_FMT_plx " len " HWADDR_FMT_plx
"\n", ppc_hash32_hpt_base(cpu),
ppc_hash32_hpt_mask(cpu) + 0x80);
for (curaddr = ppc_hash32_hpt_base(cpu);
a2 = ldl_phys(cs->as, curaddr + 8);
a3 = ldl_phys(cs->as, curaddr + 12);
if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) {
- qemu_log(TARGET_FMT_plx ": %08x %08x %08x %08x\n",
+ qemu_log(HWADDR_FMT_plx ": %08x %08x %08x %08x\n",
curaddr, a0, a1, a2, a3);
}
}
if (ret >= 0) {
ctx->raddr = raddr;
qemu_log_mask(CPU_LOG_MMU, "%s: access granted " TARGET_FMT_lx
- " => " TARGET_FMT_plx
+ " => " HWADDR_FMT_plx
" %d %d\n", __func__, address, ctx->raddr, ctx->prot,
ret);
return 0;
}
}
qemu_log_mask(CPU_LOG_MMU, "%s: access refused " TARGET_FMT_lx
- " => " TARGET_FMT_plx
+ " => " HWADDR_FMT_plx
" %d %d\n", __func__, address, raddr, ctx->prot, ret);
return ret;
if (ret >= 0) {
ctx->raddr = raddr;
qemu_log_mask(CPU_LOG_MMU, "%s: access granted " TARGET_FMT_lx
- " => " TARGET_FMT_plx " %d %d\n", __func__,
+ " => " HWADDR_FMT_plx " %d %d\n", __func__,
address, ctx->raddr, ctx->prot, ret);
} else {
qemu_log_mask(CPU_LOG_MMU, "%s: access refused " TARGET_FMT_lx
- " => " TARGET_FMT_plx " %d %d\n", __func__,
+ " => " HWADDR_FMT_plx " %d %d\n", __func__,
address, raddr, ctx->prot, ret);
}
if (ret >= 0) {
ctx->raddr = raddr;
qemu_log_mask(CPU_LOG_MMU, "%s: access granted " TARGET_FMT_lx
- " => " TARGET_FMT_plx " %d %d\n", __func__, address,
+ " => " HWADDR_FMT_plx " %d %d\n", __func__, address,
ctx->raddr, ctx->prot, ret);
} else {
qemu_log_mask(CPU_LOG_MMU, "%s: access refused " TARGET_FMT_lx
- " => " TARGET_FMT_plx " %d %d\n", __func__, address,
+ " => " HWADDR_FMT_plx " %d %d\n", __func__, address,
raddr, ctx->prot, ret);
}
tlb->prot &= ~PAGE_VALID;
}
tlb->PID = env->spr[SPR_40x_PID]; /* PID */
- qemu_log_mask(CPU_LOG_MMU, "%s: set up TLB %d RPN " TARGET_FMT_plx
+ qemu_log_mask(CPU_LOG_MMU, "%s: set up TLB %d RPN " HWADDR_FMT_plx
" EPN " TARGET_FMT_lx " size " TARGET_FMT_lx
" prot %c%c%c%c PID %d\n", __func__,
(int)entry, tlb->RPN, tlb->EPN, tlb->size,
if (val & PPC4XX_TLBLO_WR) {
tlb->prot |= PAGE_WRITE;
}
- qemu_log_mask(CPU_LOG_MMU, "%s: set up TLB %d RPN " TARGET_FMT_plx
+ qemu_log_mask(CPU_LOG_MMU, "%s: set up TLB %d RPN " HWADDR_FMT_plx
" EPN " TARGET_FMT_lx
" size " TARGET_FMT_lx " prot %c%c%c%c PID %d\n", __func__,
(int)entry, tlb->RPN, tlb->EPN, tlb->size,
qemu_log_mask(CPU_LOG_MMU,
"%s 1st-stage address=%" VADDR_PRIx " ret %d physical "
- TARGET_FMT_plx " prot %d\n",
+ HWADDR_FMT_plx " prot %d\n",
__func__, address, ret, pa, prot);
if (ret == TRANSLATE_SUCCESS) {
qemu_log_mask(CPU_LOG_MMU,
"%s 2nd-stage address=%" VADDR_PRIx " ret %d physical "
- TARGET_FMT_plx " prot %d\n",
+ HWADDR_FMT_plx " prot %d\n",
__func__, im_address, ret, pa, prot2);
prot &= prot2;
size, access_type, mode);
qemu_log_mask(CPU_LOG_MMU,
- "%s PMP address=" TARGET_FMT_plx " ret %d prot"
+ "%s PMP address=" HWADDR_FMT_plx " ret %d prot"
" %d tlb_size " TARGET_FMT_lu "\n",
__func__, pa, ret, prot_pmp, tlb_size);
qemu_log_mask(CPU_LOG_MMU,
"%s address=%" VADDR_PRIx " ret %d physical "
- TARGET_FMT_plx " prot %d\n",
+ HWADDR_FMT_plx " prot %d\n",
__func__, address, ret, pa, prot);
if (ret == TRANSLATE_SUCCESS) {
size, access_type, mode);
qemu_log_mask(CPU_LOG_MMU,
- "%s PMP address=" TARGET_FMT_plx " ret %d prot"
+ "%s PMP address=" HWADDR_FMT_plx " ret %d prot"
" %d tlb_size " TARGET_FMT_lu "\n",
__func__, pa, ret, prot_pmp, tlb_size);
return;
}
- monitor_printf(mon, TARGET_FMT_lx " " TARGET_FMT_plx " " TARGET_FMT_lx
+ monitor_printf(mon, TARGET_FMT_lx " " HWADDR_FMT_plx " " TARGET_FMT_lx
" %c%c%c%c%c%c%c\n",
addr_canonical(va_bits, vaddr),
paddr, size,
#ifdef DEBUG_UNASSIGNED
if (is_asi) {
- printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
+ printf("Unassigned mem %s access of %d byte%s to " HWADDR_FMT_plx
" asi 0x%02x from " TARGET_FMT_lx "\n",
is_exec ? "exec" : is_write ? "write" : "read", size,
size == 1 ? "" : "s", addr, is_asi, env->pc);
} else {
- printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
+ printf("Unassigned mem %s access of %d byte%s to " HWADDR_FMT_plx
" from " TARGET_FMT_lx "\n",
is_exec ? "exec" : is_write ? "write" : "read", size,
size == 1 ? "" : "s", addr, env->pc);
CPUSPARCState *env = &cpu->env;
#ifdef DEBUG_UNASSIGNED
- printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
+ printf("Unassigned mem access to " HWADDR_FMT_plx " from " TARGET_FMT_lx
"\n", addr, env->pc);
#endif
if (likely(error_code == 0)) {
qemu_log_mask(CPU_LOG_MMU,
"Translate at %" VADDR_PRIx " -> "
- TARGET_FMT_plx ", vaddr " TARGET_FMT_lx "\n",
+ HWADDR_FMT_plx ", vaddr " TARGET_FMT_lx "\n",
address, paddr, vaddr);
tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size);
return true;
hwaddr pa;
uint32_t pde;
- qemu_printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
+ qemu_printf("Root ptr: " HWADDR_FMT_plx ", ctx: %d\n",
(hwaddr)env->mmuregs[1] << 4, env->mmuregs[2]);
for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
pde = mmu_probe(env, va, 2);
if (pde) {
pa = cpu_get_phys_page_debug(cs, va);
- qemu_printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
+ qemu_printf("VA: " TARGET_FMT_lx ", PA: " HWADDR_FMT_plx
" PDE: " TARGET_FMT_lx "\n", va, pa, pde);
for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
pde = mmu_probe(env, va1, 1);
if (pde) {
pa = cpu_get_phys_page_debug(cs, va1);
qemu_printf(" VA: " TARGET_FMT_lx ", PA: "
- TARGET_FMT_plx " PDE: " TARGET_FMT_lx "\n",
+ HWADDR_FMT_plx " PDE: " TARGET_FMT_lx "\n",
va1, pa, pde);
for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
pde = mmu_probe(env, va2, 0);
if (pde) {
pa = cpu_get_phys_page_debug(cs, va2);
qemu_printf(" VA: " TARGET_FMT_lx ", PA: "
- TARGET_FMT_plx " PTE: "
+ HWADDR_FMT_plx " PTE: "
TARGET_FMT_lx "\n",
va2, pa, pde);
}
address, rw, mmu_idx);
qemu_log_mask(CPU_LOG_MMU, "%s address=" TARGET_FMT_lx " ret %d physical "
- TARGET_FMT_plx " prot %d\n",
+ HWADDR_FMT_plx " prot %d\n",
__func__, (target_ulong)address, ret, physical, prot);
if (ret == TLBRET_MATCH) {
projects / qemu.git / commitdiff