pinctrl: sunxi: Support the 2.5V I/O bias mode

H616 and newer SoCs feature a 2.5V I/O bias mode in addition to the
1.8V and 3.3V modes. This mode is entered by selecting the 3.3V level
and disabling the "withstand function".

H616 supports this capability on its main PIO only. A100 supports this
capability on both its PIO and R-PIO.

Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20220713025233.27248-4-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c
index 21054fcacd345fe6fcc7a5c71f462247216f2f21..afc1f5df75450bb5810f482966932bb4b0702aa1 100644 (file)
--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c
@@ -82,6 +82,7 @@ static const struct sunxi_pinctrl_desc a100_r_pinctrl_data = {
        .npins = ARRAY_SIZE(a100_r_pins),
        .pin_base = PL_BASE,
        .irq_banks = 1,
+       .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_CTL,
 };
 
 static int a100_r_pinctrl_probe(struct platform_device *pdev)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
index e69f6da40dc0a24ab099e999c66c237bf372a48f..f682e0e4244d219de16b0246677e2210d34b7902 100644 (file)
--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
@@ -684,7 +684,7 @@ static const struct sunxi_pinctrl_desc a100_pinctrl_data = {
        .npins = ARRAY_SIZE(a100_pins),
        .irq_banks = 7,
        .irq_bank_map = a100_irq_bank_map,
-       .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
+       .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_CTL,
 };
 
 static int a100_pinctrl_probe(struct platform_device *pdev)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c
index 152b71226a807f8c559e5a36e619de9aa75f17c2..d6ca720ee8d847ee1f8d161971ca647d796931d4 100644 (file)
--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c
@@ -525,7 +525,7 @@ static const struct sunxi_pinctrl_desc h616_pinctrl_data = {
        .irq_banks = ARRAY_SIZE(h616_irq_bank_map),
        .irq_bank_map = h616_irq_bank_map,
        .irq_read_needs_mux = true,
-       .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
+       .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_CTL,
 };
 
 static int h616_pinctrl_probe(struct platform_device *pdev)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 3c5e71359ca8d4360a528e9240da7302cf59e70d..eb3d595f816ac4b2062a10f6be00ae82c7e92044 100644 (file)
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -662,6 +662,16 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
                reg &= ~IO_BIAS_MASK;
                writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));
                return 0;
+       case BIAS_VOLTAGE_PIO_POW_MODE_CTL:
+               val = uV > 1800000 && uV <= 2500000 ? BIT(bank) : 0;
+
+               raw_spin_lock_irqsave(&pctl->lock, flags);
+               reg = readl(pctl->membase + PIO_POW_MOD_CTL_REG);
+               reg &= ~BIT(bank);
+               writel(reg | val, pctl->membase + PIO_POW_MOD_CTL_REG);
+               raw_spin_unlock_irqrestore(&pctl->lock, flags);
+
+               fallthrough;
        case BIAS_VOLTAGE_PIO_POW_MODE_SEL:
                val = uV <= 1800000 ? 1 : 0;
 

diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
index a32bb5bcb754762400a48caefc8eda090435c0eb..0f1aab58650c7fea5f519cf24208bfd21e90afc3 100644 (file)
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
@@ -98,6 +98,7 @@
 #define PINCTRL_SUN8I_V3S      BIT(10)
 
 #define PIO_POW_MOD_SEL_REG    0x340
+#define PIO_POW_MOD_CTL_REG    0x344
 
 enum sunxi_desc_bias_voltage {
        BIAS_VOLTAGE_NONE,
@@ -111,6 +112,12 @@ enum sunxi_desc_bias_voltage {
         * register, as seen on H6 SoC, for example.
         */
        BIAS_VOLTAGE_PIO_POW_MODE_SEL,
+       /*
+        * Bias voltage is set through PIO_POW_MOD_SEL_REG
+        * and PIO_POW_MOD_CTL_REG register, as seen on
+        * A100 and D1 SoC, for example.
+        */
+       BIAS_VOLTAGE_PIO_POW_MODE_CTL,
 };
 
 struct sunxi_desc_function {