Merge branch 'for-next/stage1-lpa2' into for-next/core

* for-next/stage1-lpa2: (48 commits)
  : Add support for LPA2 and WXN and stage 1
  arm64/mm: Avoid ID mapping of kpti flag if it is no longer needed
  arm64/mm: Use generic __pud_free() helper in pud_free() implementation
  arm64: gitignore: ignore relacheck
  arm64: Use Signed/Unsigned enums for TGRAN{4,16,64} and VARange
  arm64: mm: Make PUD folding check in set_pud() a runtime check
  arm64: mm: add support for WXN memory translation attribute
  mm: add arch hook to validate mmap() prot flags
  arm64: defconfig: Enable LPA2 support
  arm64: Enable 52-bit virtual addressing for 4k and 16k granule configs
  arm64: kvm: avoid CONFIG_PGTABLE_LEVELS for runtime levels
  arm64: ptdump: Deal with translation levels folded at runtime
  arm64: ptdump: Disregard unaddressable VA space
  arm64: mm: Add support for folding PUDs at runtime
  arm64: kasan: Reduce minimum shadow alignment and enable 5 level paging
  arm64: mm: Add 5 level paging support to fixmap and swapper handling
  arm64: Enable LPA2 at boot if supported by the system
  arm64: mm: add LPA2 and 5 level paging support to G-to-nG conversion
  arm64: mm: Add definitions to support 5 levels of paging
  arm64: mm: Add LPA2 support to phys<->pte conversion routines
  arm64: mm: Wire up TCR.DS bit to PTE shareability fields
  ...

diff --cc arch/arm64/Kconfig
Simple merge

diff --cc arch/arm64/include/asm/assembler.h
Simple merge

diff --cc arch/arm64/include/asm/cpufeature.h
Simple merge

diff --cc arch/arm64/kernel/cpufeature.c
index 6e1cca7b2098dddca0c1ca9b6b727670d6bdad60,d380ae783b73a3795f7795480bd4da940a534dfb..d6679d8b737e3ac2d7a516d11ef7836a61f5e354
--- 1/arch/arm64/kernel/cpufeature.c
--- 2/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@@ -752,13 -719,14 +754,15 @@@ static const struct __ftr_reg_entry 
                               &id_aa64isar1_override),
        ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2,
                               &id_aa64isar2_override),
 +      ARM64_FTR_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3),
  
        /* Op1 = 0, CRn = 0, CRm = 7 */
-       ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
+       ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0,
+                              &id_aa64mmfr0_override),
        ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1,
                               &id_aa64mmfr1_override),
-       ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
+       ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2,
+                              &id_aa64mmfr2_override),
        ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3),
  
        /* Op1 = 1, CRn = 0, CRm = 0 */
@@@ -2788,14 -2701,24 +2750,32 @@@ static const struct arm64_cpu_capabilit
                .type = ARM64_CPUCAP_SYSTEM_FEATURE,
                .matches = has_lpa2,
        },
 +      {
 +              .desc = "FPMR",
 +              .type = ARM64_CPUCAP_SYSTEM_FEATURE,
 +              .capability = ARM64_HAS_FPMR,
 +              .matches = has_cpuid_feature,
 +              .cpu_enable = cpu_enable_fpmr,
 +              ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, FPMR, IMP)
 +      },
+ #ifdef CONFIG_ARM64_VA_BITS_52
+       {
+               .capability = ARM64_HAS_VA52,
+               .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
+               .matches = has_cpuid_feature,
+ #ifdef CONFIG_ARM64_64K_PAGES
+               .desc = "52-bit Virtual Addressing (LVA)",
+               ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, VARange, 52)
+ #else
+               .desc = "52-bit Virtual Addressing (LPA2)",
+ #ifdef CONFIG_ARM64_4K_PAGES
+               ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN4, 52_BIT)
+ #else
+               ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN16, 52_BIT)
+ #endif
+ #endif
+       },
+ #endif
        {},
  };
  

diff --cc arch/arm64/kernel/setup.c
Simple merge

diff --cc arch/arm64/tools/cpucaps
Simple merge

diff --cc arch/arm64/tools/sysreg
Simple merge