ARM: dts: qcom: sdx65: fix SDHCI clocks order

Bindings expect clocks to be in different order:

  qcom-sdx65-mtp.dtb: mmc@8804000: clock-names:0: 'iface' was expected
  qcom-sdx65-mtp.dtb: mmc@8804000: clock-names:1: 'core' was expected

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230924183335.49961-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
index 76edbf6758f5214ded1153e294a22cc43d21fd13..e559adaaeee7a48a6fa1430bc7dcf0ab89d6f8a8 100644 (file)
--- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
@@ -466,9 +466,9 @@
                        interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "hc_irq", "pwr_irq";
-                       clocks = <&gcc GCC_SDCC1_APPS_CLK>,
-                                <&gcc GCC_SDCC1_AHB_CLK>;
-                       clock-names = "core", "iface";
+                       clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+                                <&gcc GCC_SDCC1_APPS_CLK>;
+                       clock-names = "iface", "core";
                        status = "disabled";
                };