riscv: dts: sophgo: add sdcard support for milkv duo
authorJisheng Zhang <jszhang@kernel.org>
Sat, 17 Feb 2024 14:48:26 +0000 (22:48 +0800)
committerInochi Amaoto <inochiama@outlook.com>
Wed, 27 Mar 2024 07:43:33 +0000 (15:43 +0800)
Add sdhci dt node in SoC dtsi and enable it in milkv duo dts.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Inochi Amaoto <inochiama@outlook.com>
Link: https://lore.kernel.org/r/20240217144826.3944-1-jszhang@kernel.org
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts
arch/riscv/boot/dts/sophgo/cv18xx.dtsi

index 3af9e34b3bc75d19760064ffc82179cfc715bd71..94e64ddce8fa3f878d72750adc011c1c9e0f81d4 100644 (file)
        clock-frequency = <25000000>;
 };
 
+&sdhci0 {
+       status = "okay";
+       bus-width = <4>;
+       no-1-8-v;
+       no-mmc;
+       no-sdio;
+};
+
 &uart0 {
        status = "okay";
 };
index 2d6f4a4b1e58b4b56ac49c051af7fbc5bf9c4d12..405f4ba18392f127d6e00d921d4416c66158e386 100644 (file)
@@ -4,6 +4,7 @@
  * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
  */
 
+#include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
 / {
                #clock-cells = <0>;
        };
 
+       sdhci_clk: sdhci-clock {
+               compatible = "fixed-clock";
+               clock-frequency = <375000000>;
+               clock-output-names = "sdhci_clk";
+               #clock-cells = <0>;
+       };
+
        soc {
                compatible = "simple-bus";
                interrupt-parent = <&plic>;
                        status = "disabled";
                };
 
+               sdhci0: mmc@4310000 {
+                       compatible = "sophgo,cv1800b-dwcmshc";
+                       reg = <0x4310000 0x1000>;
+                       interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&sdhci_clk>;
+                       clock-names = "core";
+                       status = "disabled";
+               };
+
                plic: interrupt-controller@70000000 {
                        reg = <0x70000000 0x4000000>;
                        interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;