riscv: report perf event for misaligned fault
authorClément Léger <cleger@rivosinc.com>
Wed, 4 Oct 2023 15:14:00 +0000 (17:14 +0200)
committerPalmer Dabbelt <palmer@rivosinc.com>
Wed, 1 Nov 2023 15:34:54 +0000 (08:34 -0700)
Add missing calls to account for misaligned fault event using
perf_sw_event().

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Björn Töpel <bjorn@rivosinc.com>
Link: https://lore.kernel.org/r/20231004151405.521596-4-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/kernel/traps_misaligned.c

index 9daed7d756ae89677b4afb7ef6c6a4a660a63084..804f6c5e0e4492c837496da2d4fb6856814648ae 100644 (file)
@@ -6,6 +6,7 @@
 #include <linux/init.h>
 #include <linux/mm.h>
 #include <linux/module.h>
+#include <linux/perf_event.h>
 #include <linux/irq.h>
 #include <linux/stringify.h>
 
@@ -294,6 +295,8 @@ int handle_misaligned_load(struct pt_regs *regs)
        unsigned long addr = regs->badaddr;
        int i, fp = 0, shift = 0, len = 0;
 
+       perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
+
        if (get_insn(regs, epc, &insn))
                return -1;
 
@@ -382,6 +385,8 @@ int handle_misaligned_store(struct pt_regs *regs)
        unsigned long addr = regs->badaddr;
        int i, len = 0;
 
+       perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
+
        if (get_insn(regs, epc, &insn))
                return -1;