drm/msm/dpu: enable INTF TE operations only when supported by HW

The DPU_INTF_TE bit is set for all INTF blocks on DPU >= 5.0, however
only INTF_1 and INTF_2 actually support tearing control (both are
INTF_DSI). Rather than trying to limit the DPU_INTF_TE feature bit to
those two INTF instances, check for the major && INTF type.

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/555547/
Link: https://lore.kernel.org/r/20230904020454.2945667-6-dmitry.baryshkov@linaro.org

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index bf7c6e1d3ea589c77ce33ebfb3db5db683c96c42..e8b8908d3e122671fc1f49dabbad5598805bf44a 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -561,7 +561,10 @@ struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg,
        if (cfg->features & BIT(DPU_INTF_INPUT_CTRL))
                c->ops.bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk;
 
-       if (cfg->features & BIT(DPU_INTF_TE)) {
+       /* INTF TE is only for DSI interfaces */
+       if (mdss_rev->core_major_ver >= 5 && cfg->type == INTF_DSI) {
+               WARN_ON(!cfg->intr_tear_rd_ptr);
+
                c->ops.enable_tearcheck = dpu_hw_intf_enable_te;
                c->ops.disable_tearcheck = dpu_hw_intf_disable_te;
                c->ops.connect_external_te = dpu_hw_intf_connect_external_te;