iommu/vt-d: Fix to flush cache of PASID directory table
authorYanfei Xu <yanfei.xu@intel.com>
Wed, 9 Aug 2023 12:48:04 +0000 (20:48 +0800)
committerJoerg Roedel <jroedel@suse.de>
Wed, 9 Aug 2023 15:46:19 +0000 (17:46 +0200)
Even the PCI devices don't support pasid capability, PASID table is
mandatory for a PCI device in scalable mode. However flushing cache
of pasid directory table for these devices are not taken after pasid
table is allocated as the "size" of table is zero. Fix it by
calculating the size by page order.

Found this when reading the code, no real problem encountered for now.

Fixes: 194b3348bdbb ("iommu/vt-d: Fix PASID directory pointer coherency")
Suggested-by: Lu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: Yanfei Xu <yanfei.xu@intel.com>
Link: https://lore.kernel.org/r/20230616081045.721873-1-yanfei.xu@intel.com
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
drivers/iommu/intel/pasid.c

index 23dca3bc319d867a0ac02345849d300393bdba28..8f92b92f3d2aba5ce2455fcf8d3604ea4eeee4ae 100644 (file)
@@ -129,7 +129,7 @@ int intel_pasid_alloc_table(struct device *dev)
        info->pasid_table = pasid_table;
 
        if (!ecap_coherent(info->iommu->ecap))
-               clflush_cache_range(pasid_table->table, size);
+               clflush_cache_range(pasid_table->table, (1 << order) * PAGE_SIZE);
 
        return 0;
 }