};
 
                memory-controller@2000 {
-                       compatible = "fsl,8540-memory-controller";
+                       compatible = "fsl,mpc8540-memory-controller";
                        reg = <0x2000 0x1000>;
                        interrupt-parent = <&mpic>;
                        interrupts = <18 2>;
                };
 
                L2: l2-cache-controller@20000 {
-                       compatible = "fsl,8540-l2-cache-controller";
+                       compatible = "fsl,mpc8540-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>; // 32 bytes
                        cache-size = <0x40000>; // L2, 256K
 
                };
 
                memory-controller@2000 {
-                       compatible = "fsl,8541-memory-controller";
+                       compatible = "fsl,mpc8541-memory-controller";
                        reg = <0x2000 0x1000>;
                        interrupt-parent = <&mpic>;
                        interrupts = <18 2>;
                };
 
                L2: l2-cache-controller@20000 {
-                       compatible = "fsl,8541-l2-cache-controller";
+                       compatible = "fsl,mpc8541-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>; // 32 bytes
                        cache-size = <0x40000>; // L2, 256K
 
                };
 
                memory-controller@2000 {
-                       compatible = "fsl,8544-memory-controller";
+                       compatible = "fsl,mpc8544-memory-controller";
                        reg = <0x2000 0x1000>;
                        interrupt-parent = <&mpic>;
                        interrupts = <18 2>;
                };
 
                L2: l2-cache-controller@20000 {
-                       compatible = "fsl,8544-l2-cache-controller";
+                       compatible = "fsl,mpc8544-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>; // 32 bytes
                        cache-size = <0x40000>; // L2, 256K
 
                };
 
                memory-controller@2000 {
-                       compatible = "fsl,8548-memory-controller";
+                       compatible = "fsl,mpc8548-memory-controller";
                        reg = <0x2000 0x1000>;
                        interrupt-parent = <&mpic>;
                        interrupts = <18 2>;
                };
 
                L2: l2-cache-controller@20000 {
-                       compatible = "fsl,8548-l2-cache-controller";
+                       compatible = "fsl,mpc8548-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>; // 32 bytes
                        cache-size = <0x80000>; // L2, 512K
 
                };
 
                memory-controller@2000 {
-                       compatible = "fsl,8555-memory-controller";
+                       compatible = "fsl,mpc8555-memory-controller";
                        reg = <0x2000 0x1000>;
                        interrupt-parent = <&mpic>;
                        interrupts = <18 2>;
                };
 
                L2: l2-cache-controller@20000 {
-                       compatible = "fsl,8555-l2-cache-controller";
+                       compatible = "fsl,mpc8555-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>; // 32 bytes
                        cache-size = <0x40000>; // L2, 256K
 
                };
 
                memory-controller@2000 {
-                       compatible = "fsl,8540-memory-controller";
+                       compatible = "fsl,mpc8540-memory-controller";
                        reg = <0x2000 0x1000>;
                        interrupt-parent = <&mpic>;
                        interrupts = <18 2>;
                };
 
                L2: l2-cache-controller@20000 {
-                       compatible = "fsl,8540-l2-cache-controller";
+                       compatible = "fsl,mpc8540-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>; // 32 bytes
                        cache-size = <0x40000>; // L2, 256K
 
                };
 
                memory-controller@2000 {
-                       compatible = "fsl,8568-memory-controller";
+                       compatible = "fsl,mpc8568-memory-controller";
                        reg = <0x2000 0x1000>;
                        interrupt-parent = <&mpic>;
                        interrupts = <18 2>;
                };
 
                L2: l2-cache-controller@20000 {
-                       compatible = "fsl,8568-l2-cache-controller";
+                       compatible = "fsl,mpc8568-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>; // 32 bytes
                        cache-size = <0x80000>; // L2, 512K