val = readl(ispi->base + HSFSTS_CTL);
val &= ~(HSFSTS_CTL_FCYCLE_MASK | HSFSTS_CTL_FDBC_MASK);
-
- if (len > INTEL_SPI_FIFO_SZ)
- return -EINVAL;
-
val |= (len - 1) << HSFSTS_CTL_FDBC_SHIFT;
val |= HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
val |= HSFSTS_CTL_FGO;
if (ret < 0)
return ret;
- if (len > INTEL_SPI_FIFO_SZ)
- return -EINVAL;
-
/*
* Always clear it after each SW sequencer operation regardless
* of whether it is successful or not.
return 0;
}
+static int intel_spi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
+{
+ op->data.nbytes = clamp_val(op->data.nbytes, 0, INTEL_SPI_FIFO_SZ);
+ return 0;
+}
+
static bool intel_spi_cmp_mem_op(const struct intel_spi_mem_op *iop,
const struct spi_mem_op *op)
{
}
static const struct spi_controller_mem_ops intel_spi_mem_ops = {
+ .adjust_op_size = intel_spi_adjust_op_size,
.supports_op = intel_spi_supports_mem_op,
.exec_op = intel_spi_exec_mem_op,
.get_name = intel_spi_get_name,