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docs/cxl: Fix sentence
author
Stefan Weil
<sw@weilnetz.de>
Sun, 9 Apr 2023 20:18:28 +0000
(22:18 +0200)
committer
Michael S. Tsirkin
<mst@redhat.com>
Tue, 25 Apr 2023 02:56:55 +0000
(22:56 -0400)
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Message-Id: <
20230409201828
.
1159568
-1-sw@weilnetz.de>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
docs/system/devices/cxl.rst
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diff --git
a/docs/system/devices/cxl.rst
b/docs/system/devices/cxl.rst
index f25783a4ecf06d583c02342ef2dee9e5c7b2b0da..4c3822306984c82deeef5c033e03b77aa7681bfa 100644
(file)
--- a/
docs/system/devices/cxl.rst
+++ b/
docs/system/devices/cxl.rst
@@
-111,7
+111,7
@@
Interfaces provided include:
CXL Root Ports (CXL RP)
~~~~~~~~~~~~~~~~~~~~~~~
-A CXL Root Port serve
rs t
e same purpose as a PCIe Root Port.
+A CXL Root Port serve
s th
e same purpose as a PCIe Root Port.
There are a number of CXL specific Designated Vendor Specific
Extended Capabilities (DVSEC) in PCIe Configuration Space
and associated component register access via PCI bars.