pinctrl: renesas: r8a779f0: Add MSIOF pins, groups, and functions

Add pins, groups, and function for the Clock-Synchronized Serial
Interfaces with FIFO (MSIOF) on the Renesas R-Car S4-8 (R8A779F0) SoC.

Based on a larger patch in the BSP by LUU HOAI.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/c625769714b1027a756dd2ed4a017eb24708a041.1645457792.git.geert+renesas@glider.be

diff --git a/drivers/pinctrl/renesas/pfc-r8a779f0.c b/drivers/pinctrl/renesas/pfc-r8a779f0.c
index 6fbe42e891dda4e35043b5b8ee87bed3811b3d7e..047641653a7fe0e634b4b6ad04250da1cc4766d2 100644 (file)
--- a/drivers/pinctrl/renesas/pfc-r8a779f0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779f0.c
@@ -722,6 +722,182 @@ static const unsigned int mmc_ds_mux[] = {
        MMC_DS_MARK,
 };
 
+/* - MSIOF0 ----------------------------------------------------------------- */
+static const unsigned int msiof0_clk_pins[] = {
+       /* MSIOF0_SCK */
+       RCAR_GP_PIN(0, 14),
+};
+static const unsigned int msiof0_clk_mux[] = {
+       MSIOF0_SCK_MARK,
+};
+static const unsigned int msiof0_sync_pins[] = {
+       /* MSIOF0_SYNC */
+       RCAR_GP_PIN(0, 11),
+};
+static const unsigned int msiof0_sync_mux[] = {
+       MSIOF0_SYNC_MARK,
+};
+static const unsigned int msiof0_ss1_pins[] = {
+       /* MSIOF0_SS1 */
+       RCAR_GP_PIN(0, 15),
+};
+static const unsigned int msiof0_ss1_mux[] = {
+       MSIOF0_SS1_MARK,
+};
+static const unsigned int msiof0_ss2_pins[] = {
+       /* MSIOF0_SS2 */
+       RCAR_GP_PIN(0, 16),
+};
+static const unsigned int msiof0_ss2_mux[] = {
+       MSIOF0_SS2_MARK,
+};
+static const unsigned int msiof0_txd_pins[] = {
+       /* MSIOF0_TXD */
+       RCAR_GP_PIN(0, 13),
+};
+static const unsigned int msiof0_txd_mux[] = {
+       MSIOF0_TXD_MARK,
+};
+static const unsigned int msiof0_rxd_pins[] = {
+       /* MSIOF0_RXD */
+       RCAR_GP_PIN(0, 12),
+};
+static const unsigned int msiof0_rxd_mux[] = {
+       MSIOF0_RXD_MARK,
+};
+
+/* - MSIOF1 ----------------------------------------------------------------- */
+static const unsigned int msiof1_clk_pins[] = {
+       /* MSIOF1_SCK */
+       RCAR_GP_PIN(0, 8),
+};
+static const unsigned int msiof1_clk_mux[] = {
+       MSIOF1_SCK_MARK,
+};
+static const unsigned int msiof1_sync_pins[] = {
+       /* MSIOF1_SYNC */
+       RCAR_GP_PIN(0, 10),
+};
+static const unsigned int msiof1_sync_mux[] = {
+       MSIOF1_SYNC_MARK,
+};
+static const unsigned int msiof1_ss1_pins[] = {
+       /* MSIOF1_SS1 */
+       RCAR_GP_PIN(0, 17),
+};
+static const unsigned int msiof1_ss1_mux[] = {
+       MSIOF1_SS1_MARK,
+};
+static const unsigned int msiof1_ss2_pins[] = {
+       /* MSIOF1_SS2 */
+       RCAR_GP_PIN(0, 18),
+};
+static const unsigned int msiof1_ss2_mux[] = {
+       MSIOF1_SS2_MARK,
+};
+static const unsigned int msiof1_txd_pins[] = {
+       /* MSIOF1_TXD */
+       RCAR_GP_PIN(0, 7),
+};
+static const unsigned int msiof1_txd_mux[] = {
+       MSIOF1_TXD_MARK,
+};
+static const unsigned int msiof1_rxd_pins[] = {
+       /* MSIOF1_RXD */
+       RCAR_GP_PIN(0, 6),
+};
+static const unsigned int msiof1_rxd_mux[] = {
+       MSIOF1_RXD_MARK,
+};
+
+/* - MSIOF2 ----------------------------------------------------------------- */
+static const unsigned int msiof2_clk_pins[] = {
+       /* MSIOF2_SCK */
+       RCAR_GP_PIN(1, 5),
+};
+static const unsigned int msiof2_clk_mux[] = {
+       MSIOF2_SCK_MARK,
+};
+static const unsigned int msiof2_sync_pins[] = {
+       /* MSIOF2_SYNC */
+       RCAR_GP_PIN(1, 4),
+};
+static const unsigned int msiof2_sync_mux[] = {
+       MSIOF2_SYNC_MARK,
+};
+static const unsigned int msiof2_ss1_pins[] = {
+       /* MSIOF2_SS1 */
+       RCAR_GP_PIN(1, 2),
+};
+static const unsigned int msiof2_ss1_mux[] = {
+       MSIOF2_SS1_MARK,
+};
+static const unsigned int msiof2_ss2_pins[] = {
+       /* MSIOF2_SS2 */
+       RCAR_GP_PIN(1, 3),
+};
+static const unsigned int msiof2_ss2_mux[] = {
+       MSIOF2_SS2_MARK,
+};
+static const unsigned int msiof2_txd_pins[] = {
+       /* MSIOF2_TXD */
+       RCAR_GP_PIN(1, 7),
+};
+static const unsigned int msiof2_txd_mux[] = {
+       MSIOF2_TXD_MARK,
+};
+static const unsigned int msiof2_rxd_pins[] = {
+       /* MSIOF2_RXD */
+       RCAR_GP_PIN(1, 6),
+};
+static const unsigned int msiof2_rxd_mux[] = {
+       MSIOF2_RXD_MARK,
+};
+
+/* - MSIOF3 ----------------------------------------------------------------- */
+static const unsigned int msiof3_clk_pins[] = {
+       /* MSIOF3_SCK */
+       RCAR_GP_PIN(0, 1),
+};
+static const unsigned int msiof3_clk_mux[] = {
+       MSIOF3_SCK_MARK,
+};
+static const unsigned int msiof3_sync_pins[] = {
+       /* MSIOF3_SYNC */
+       RCAR_GP_PIN(0, 9),
+};
+static const unsigned int msiof3_sync_mux[] = {
+       MSIOF3_SYNC_MARK,
+};
+static const unsigned int msiof3_ss1_pins[] = {
+       /* MSIOF3_SS1 */
+       RCAR_GP_PIN(0, 4),
+};
+static const unsigned int msiof3_ss1_mux[] = {
+       MSIOF3_SS1_MARK,
+};
+static const unsigned int msiof3_ss2_pins[] = {
+       /* MSIOF3_SS2 */
+       RCAR_GP_PIN(0, 5),
+};
+static const unsigned int msiof3_ss2_mux[] = {
+       MSIOF3_SS2_MARK,
+};
+static const unsigned int msiof3_txd_pins[] = {
+       /* MSIOF3_TXD */
+       RCAR_GP_PIN(0, 3),
+};
+static const unsigned int msiof3_txd_mux[] = {
+       MSIOF3_TXD_MARK,
+};
+static const unsigned int msiof3_rxd_pins[] = {
+       /* MSIOF3_RXD */
+       RCAR_GP_PIN(0, 2),
+};
+static const unsigned int msiof3_rxd_mux[] = {
+       MSIOF3_RXD_MARK,
+};
+
 /* - SCIF0 ------------------------------------------------------------------ */
 static const unsigned int scif0_data_pins[] = {
        /* RX0, TX0 */
@@ -855,6 +1031,30 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
        SH_PFC_PIN_GROUP(mmc_cd),
        SH_PFC_PIN_GROUP(mmc_wp),
        SH_PFC_PIN_GROUP(mmc_ds),
+       SH_PFC_PIN_GROUP(msiof0_clk),
+       SH_PFC_PIN_GROUP(msiof0_sync),
+       SH_PFC_PIN_GROUP(msiof0_ss1),
+       SH_PFC_PIN_GROUP(msiof0_ss2),
+       SH_PFC_PIN_GROUP(msiof0_txd),
+       SH_PFC_PIN_GROUP(msiof0_rxd),
+       SH_PFC_PIN_GROUP(msiof1_clk),
+       SH_PFC_PIN_GROUP(msiof1_sync),
+       SH_PFC_PIN_GROUP(msiof1_ss1),
+       SH_PFC_PIN_GROUP(msiof1_ss2),
+       SH_PFC_PIN_GROUP(msiof1_txd),
+       SH_PFC_PIN_GROUP(msiof1_rxd),
+       SH_PFC_PIN_GROUP(msiof2_clk),
+       SH_PFC_PIN_GROUP(msiof2_sync),
+       SH_PFC_PIN_GROUP(msiof2_ss1),
+       SH_PFC_PIN_GROUP(msiof2_ss2),
+       SH_PFC_PIN_GROUP(msiof2_txd),
+       SH_PFC_PIN_GROUP(msiof2_rxd),
+       SH_PFC_PIN_GROUP(msiof3_clk),
+       SH_PFC_PIN_GROUP(msiof3_sync),
+       SH_PFC_PIN_GROUP(msiof3_ss1),
+       SH_PFC_PIN_GROUP(msiof3_ss2),
+       SH_PFC_PIN_GROUP(msiof3_txd),
+       SH_PFC_PIN_GROUP(msiof3_rxd),
        SH_PFC_PIN_GROUP(scif0_data),
        SH_PFC_PIN_GROUP(scif0_clk),
        SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -937,6 +1137,42 @@ static const char * const mmc_groups[] = {
        "mmc_ds",
 };
 
+static const char * const msiof0_groups[] = {
+       "msiof0_clk",
+       "msiof0_sync",
+       "msiof0_ss1",
+       "msiof0_ss2",
+       "msiof0_txd",
+       "msiof0_rxd",
+};
+
+static const char * const msiof1_groups[] = {
+       "msiof1_clk",
+       "msiof1_sync",
+       "msiof1_ss1",
+       "msiof1_ss2",
+       "msiof1_txd",
+       "msiof1_rxd",
+};
+
+static const char * const msiof2_groups[] = {
+       "msiof2_clk",
+       "msiof2_sync",
+       "msiof2_ss1",
+       "msiof2_ss2",
+       "msiof2_txd",
+       "msiof2_rxd",
+};
+
+static const char * const msiof3_groups[] = {
+       "msiof3_clk",
+       "msiof3_sync",
+       "msiof3_ss1",
+       "msiof3_ss2",
+       "msiof3_txd",
+       "msiof3_rxd",
+};
+
 static const char * const scif0_groups[] = {
        "scif0_data",
        "scif0_clk",
@@ -978,6 +1214,10 @@ static const struct sh_pfc_function pinmux_functions[] = {
        SH_PFC_FUNCTION(i2c5),
        SH_PFC_FUNCTION(intc_ex),
        SH_PFC_FUNCTION(mmc),
+       SH_PFC_FUNCTION(msiof0),
+       SH_PFC_FUNCTION(msiof1),
+       SH_PFC_FUNCTION(msiof2),
+       SH_PFC_FUNCTION(msiof3),
        SH_PFC_FUNCTION(scif0),
        SH_PFC_FUNCTION(scif1),
        SH_PFC_FUNCTION(scif3),