bool align_bdle_4k:1;           /* BDLE align 4K boundary */
        bool reverse_assign:1;          /* assign devices in reverse order */
        bool corbrp_self_clear:1;       /* CORBRP clears itself after reset */
+       bool polling_mode:1;
+
+       int poll_count;
 
        int bdl_pos_adj;                /* BDL position adjustment */
 
 
 
        for (loopcounter = 0;; loopcounter++) {
                spin_lock_irq(&bus->reg_lock);
-               if (chip->polling_mode || do_poll)
+               if (bus->polling_mode || do_poll)
                        snd_hdac_bus_update_rirb(bus);
                if (!bus->rirb.cmds[addr]) {
                        if (!do_poll)
-                               chip->poll_count = 0;
+                               bus->poll_count = 0;
                        if (res)
                                *res = bus->rirb.res[addr]; /* the last value */
                        spin_unlock_irq(&bus->reg_lock);
        if (hbus->no_response_fallback)
                return -EIO;
 
-       if (!chip->polling_mode && chip->poll_count < 2) {
+       if (!bus->polling_mode && bus->poll_count < 2) {
                dev_dbg(chip->card->dev,
                        "azx_get_response timeout, polling the codec once: last cmd=0x%08x\n",
                        bus->last_cmd[addr]);
                do_poll = 1;
-               chip->poll_count++;
+               bus->poll_count++;
                goto again;
        }
 
 
-       if (!chip->polling_mode) {
+       if (!bus->polling_mode) {
                dev_warn(chip->card->dev,
                         "azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n",
                         bus->last_cmd[addr]);
-               chip->polling_mode = 1;
+               bus->polling_mode = 1;
                goto again;
        }
 
 
 
        /* flags */
        int bdl_pos_adj;
-       int poll_count;
        unsigned int running:1;
        unsigned int fallback_to_single_cmd:1;
        unsigned int single_cmd:1;
-       unsigned int polling_mode:1;
        unsigned int msi:1;
        unsigned int probing:1; /* codec probing phase */
        unsigned int snoop:1;
 
 
        /* Workaround for a communication error on CFL (bko#199007) and CNL */
        if (IS_CFL(pci) || IS_CNL(pci))
-               chip->polling_mode = 1;
+               azx_bus(chip)->polling_mode = 1;
 
        if (chip->driver_type == AZX_DRIVER_NVIDIA) {
                dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");