arm64: dts: qcom: msm8998: switch PCIe QMP PHY to new style of bindings

Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230820142035.89903-11-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index aac23a8ef6c8e2415083d6dc8c65846c399eb217..b485bf925ce613e408ad21940e806fdf7ed4335f 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -946,7 +946,7 @@
                        #address-cells = <3>;
                        #size-cells = <2>;
                        num-lanes = <1>;
-                       phys = <&pciephy>;
+                       phys = <&pcie_phy>;
                        phy-names = "pciephy";
                        status = "disabled";
 
@@ -976,32 +976,28 @@
 
                pcie_phy: phy@1c06000 {
                        compatible = "qcom,msm8998-qmp-pcie-phy";
-                       reg = <0x01c06000 0x18c>;
-                       #address-cells = <1>;
-                       #size-cells = <1>;
+                       reg = <0x01c06000 0x1000>;
                        status = "disabled";
-                       ranges;
 
                        clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
                                 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
-                                <&gcc GCC_PCIE_CLKREF_CLK>;
-                       clock-names = "aux", "cfg_ahb", "ref";
+                                <&gcc GCC_PCIE_CLKREF_CLK>,
+                                <&gcc GCC_PCIE_0_PIPE_CLK>;
+                       clock-names = "aux",
+                                     "cfg_ahb",
+                                     "ref",
+                                     "pipe";
+
+                       clock-output-names = "pcie_0_pipe_clk_src";
+                       #clock-cells = <0>;
+
+                       #phy-cells = <0>;
 
                        resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
                        reset-names = "phy", "common";
 
                        vdda-phy-supply = <&vreg_l1a_0p875>;
                        vdda-pll-supply = <&vreg_l2a_1p2>;
-
-                       pciephy: phy@1c06800 {
-                               reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>;
-                               #phy-cells = <0>;
-
-                               clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
-                               clock-names = "pipe0";
-                               clock-output-names = "pcie_0_pipe_clk_src";
-                               #clock-cells = <0>;
-                       };
                };
 
                ufshc: ufshc@1da4000 {