projects
/
linux.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
5f2a9cd
)
arm64: dts: qcom: x1e80100: Add TCSR node
author
Abel Vesa
<abel.vesa@linaro.org>
Mon, 29 Jan 2024 12:45:37 +0000
(14:45 +0200)
committer
Bjorn Andersson
<andersson@kernel.org>
Tue, 6 Feb 2024 17:14:29 +0000
(11:14 -0600)
Add the TCSR clock controller and register space node.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link:
https://lore.kernel.org/r/20240129-x1e80100-dts-missing-nodes-v6-5-2c0e691cfa3b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
arch/arm64/boot/dts/qcom/x1e80100.dtsi
patch
|
blob
|
history
diff --git
a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 22ba653714f4b37ecdc83ae9c2dca70a1048f9e4..54827eaca7464dfe83f03e677ef3ed0a55ec5154 100644
(file)
--- a/
arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/
arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@
-2614,6
+2614,14
@@
#hwlock-cells = <1>;
};
+ tcsr: clock-controller@1fc0000 {
+ compatible = "qcom,x1e80100-tcsr", "syscon";
+ reg = <0 0x01fc0000 0 0x30000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
gem_noc: interconnect@26400000 {
compatible = "qcom,x1e80100-gem-noc";
reg = <0 0x26400000 0 0x311200>;