DPRINTF("Switching to %dx%d %d %d @ %x\n", h, v, stride, bpp, offs);
vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE);
vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_DISABLED);
- s->vga.big_endian_fb = false;
+ s->vga.big_endian_fb = (s->regs.config_cntl & APER_0_ENDIAN ||
+ s->regs.config_cntl & APER_1_ENDIAN ?
+ true : false);
/* reset VBE regs then set up mode */
s->vga.vbe_regs[VBE_DISPI_INDEX_XRES] = h;
s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] = v;
case PALETTE_DATA:
val = vga_ioport_read(&s->vga, VGA_PEL_D);
break;
+ case CNFG_CNTL:
+ val = s->regs.config_cntl;
+ break;
case CNFG_MEMSIZE:
val = s->vga.vram_size;
break;
data >>= 8;
vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff);
break;
+ case CNFG_CNTL:
+ s->regs.config_cntl = data;
+ break;
case CRTC_H_TOTAL_DISP:
s->regs.crtc_h_total_disp = data & 0x07ff07ff;
break;
#define X_MPLL_REF_DIV_MASK 0x000000FF
/* Config control values (CONFIG_CNTL) */
+#define APER_0_ENDIAN 0x00000003
+#define APER_1_ENDIAN 0x0000000c
#define CFG_VGA_IO_DIS 0x00000400
/* CRTC control values (CRTC_GEN_CNTL) */