INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ,
                                ARRAY_SIZE(AR9462_BBC_TXIFR_COEFFJ), 2);
+       } else if (AR_SREV_9550(ah)) {
+               /* mac */
+               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+                               ar955x_1p0_mac_core,
+                               ARRAY_SIZE(ar955x_1p0_mac_core), 2);
+               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+                               ar955x_1p0_mac_postamble,
+                               ARRAY_SIZE(ar955x_1p0_mac_postamble), 5);
+
+               /* bb */
+               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+                               ar955x_1p0_baseband_core,
+                               ARRAY_SIZE(ar955x_1p0_baseband_core), 2);
+               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+                               ar955x_1p0_baseband_postamble,
+                               ARRAY_SIZE(ar955x_1p0_baseband_postamble), 5);
+
+               /* radio */
+               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+                               ar955x_1p0_radio_core,
+                               ARRAY_SIZE(ar955x_1p0_radio_core), 2);
+               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+                               ar955x_1p0_radio_postamble,
+                               ARRAY_SIZE(ar955x_1p0_radio_postamble), 5);
+
+               /* soc */
+               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+                               ar955x_1p0_soc_preamble,
+                               ARRAY_SIZE(ar955x_1p0_soc_preamble), 2);
+               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
+               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+                               ar955x_1p0_soc_postamble,
+                               ARRAY_SIZE(ar955x_1p0_soc_postamble), 5);
 
+               /* rx/tx gain */
+               INIT_INI_ARRAY(&ah->iniModesRxGain,
+                       ar955x_1p0_common_wo_xlna_rx_gain_table,
+                       ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_table),
+                       2);
+               INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
+                       ar955x_1p0_common_wo_xlna_rx_gain_bounds,
+                       ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_bounds),
+                       5);
+               INIT_INI_ARRAY(&ah->iniModesTxGain,
+                               ar955x_1p0_modes_xpa_tx_gain_table,
+                               ARRAY_SIZE(ar955x_1p0_modes_xpa_tx_gain_table),
+                               9);
+
+               /* Fast clock modal settings */
+               INIT_INI_ARRAY(&ah->iniModesFastClock,
+                               ar955x_1p0_modes_fast_clock,
+                               ARRAY_SIZE(ar955x_1p0_modes_fast_clock), 3);
        } else if (AR_SREV_9580(ah)) {
                /* mac */
                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
                        ar9485_modes_lowest_ob_db_tx_gain_1_1,
                        ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
                        5);
+       else if (AR_SREV_9550(ah))
+               INIT_INI_ARRAY(&ah->iniModesTxGain,
+                       ar955x_1p0_modes_xpa_tx_gain_table,
+                       ARRAY_SIZE(ar955x_1p0_modes_xpa_tx_gain_table),
+                       9);
        else if (AR_SREV_9580(ah))
                INIT_INI_ARRAY(&ah->iniModesTxGain,
                        ar9580_1p0_lowest_ob_db_tx_gain_table,
                        ar9580_1p0_high_ob_db_tx_gain_table,
                        ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table),
                        5);
+       else if (AR_SREV_9550(ah))
+               INIT_INI_ARRAY(&ah->iniModesTxGain,
+                       ar955x_1p0_modes_no_xpa_tx_gain_table,
+                       ARRAY_SIZE(ar955x_1p0_modes_no_xpa_tx_gain_table),
+                       9);
        else if (AR_SREV_9462_20(ah))
                INIT_INI_ARRAY(&ah->iniModesTxGain,
                        ar9462_modes_high_ob_db_tx_gain_table_2p0,
                                ar9485Common_wo_xlna_rx_gain_1_1,
                                ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
                                2);
-       else if (AR_SREV_9580(ah))
+       else if (AR_SREV_9550(ah)) {
+               INIT_INI_ARRAY(&ah->iniModesRxGain,
+                               ar955x_1p0_common_rx_gain_table,
+                               ARRAY_SIZE(ar955x_1p0_common_rx_gain_table),
+                               2);
+               INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
+                               ar955x_1p0_common_rx_gain_bounds,
+                               ARRAY_SIZE(ar955x_1p0_common_rx_gain_bounds),
+                               5);
+       } else if (AR_SREV_9580(ah))
                INIT_INI_ARRAY(&ah->iniModesRxGain,
                                ar9580_1p0_rx_gain_table,
                                ARRAY_SIZE(ar9580_1p0_rx_gain_table),
                        ar9462_common_wo_xlna_rx_gain_table_2p0,
                        ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_2p0),
                        2);
-       else if (AR_SREV_9580(ah))
+       else if (AR_SREV_9550(ah)) {
+               INIT_INI_ARRAY(&ah->iniModesRxGain,
+                       ar955x_1p0_common_wo_xlna_rx_gain_table,
+                       ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_table),
+                       2);
+               INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
+                       ar955x_1p0_common_wo_xlna_rx_gain_bounds,
+                       ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_bounds),
+                       5);
+       } else if (AR_SREV_9580(ah))
                INIT_INI_ARRAY(&ah->iniModesRxGain,
                        ar9580_1p0_wo_xlna_rx_gain_table,
                        ARRAY_SIZE(ar9580_1p0_wo_xlna_rx_gain_table),
 
        }
 }
 
+static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah,
+                                           struct ath9k_channel *chan)
+{
+       int ret;
+
+       switch (chan->chanmode) {
+       case CHANNEL_A:
+       case CHANNEL_A_HT20:
+               if (chan->channel <= 5350)
+                       ret = 1;
+               else if ((chan->channel > 5350) && (chan->channel <= 5600))
+                       ret = 3;
+               else
+                       ret = 5;
+               break;
+
+       case CHANNEL_A_HT40PLUS:
+       case CHANNEL_A_HT40MINUS:
+               if (chan->channel <= 5350)
+                       ret = 2;
+               else if ((chan->channel > 5350) && (chan->channel <= 5600))
+                       ret = 4;
+               else
+                       ret = 6;
+               break;
+
+       case CHANNEL_G:
+       case CHANNEL_G_HT20:
+       case CHANNEL_B:
+               ret = 8;
+               break;
+
+       case CHANNEL_G_HT40PLUS:
+       case CHANNEL_G_HT40MINUS:
+               ret = 7;
+               break;
+
+       default:
+               ret = -EINVAL;
+       }
+
+       return ret;
+}
+
 static int ar9003_hw_process_ini(struct ath_hw *ah,
                                 struct ath9k_channel *chan)
 {
        }
 
        REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
-       REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
+       if (AR_SREV_9550(ah))
+               REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex,
+                               regWrites);
+
+       if (AR_SREV_9550(ah)) {
+               int modes_txgain_index;
+
+               modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);
+               if (modes_txgain_index < 0)
+                       return -EINVAL;
+
+               REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index,
+                               regWrites);
+       } else {
+               REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
+       }
 
        /*
         * For 5GHz channels requiring Fast Clock, apply