drm/bridge: ti-sn65dsi86: Fix output polarity setting bug

According to the description in ti-sn65dsi86's datasheet:

CHA_HSYNC_POLARITY:
0 = Active High Pulse. Synchronization signal is high for the sync
pulse width. (default)
1 = Active Low Pulse. Synchronization signal is low for the sync
pulse width.

CHA_VSYNC_POLARITY:
0 = Active High Pulse. Synchronization signal is high for the sync
pulse width. (Default)
1 = Active Low Pulse. Synchronization signal is low for the sync
pulse width.

We should only set these bits when the polarity is negative.

Fixes: a095f15c00e2 ("drm/bridge: add support for sn65dsi86 bridge driver")
Signed-off-by: Qiqi Zhang <eddy.zhang@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20221125104558.84616-1-eddy.zhang@rock-chips.com

diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
index 3c3561942eb661e807cc59013d63bf91b7f28443..eb24322df721a780dc135214b395ab5bd4861a82 100644 (file)
--- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
+++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
@@ -931,9 +931,9 @@ static void ti_sn_bridge_set_video_timings(struct ti_sn65dsi86 *pdata)
                &pdata->bridge.encoder->crtc->state->adjusted_mode;
        u8 hsync_polarity = 0, vsync_polarity = 0;
 
-       if (mode->flags & DRM_MODE_FLAG_PHSYNC)
+       if (mode->flags & DRM_MODE_FLAG_NHSYNC)
                hsync_polarity = CHA_HSYNC_POLARITY;
-       if (mode->flags & DRM_MODE_FLAG_PVSYNC)
+       if (mode->flags & DRM_MODE_FLAG_NVSYNC)
                vsync_polarity = CHA_VSYNC_POLARITY;
 
        ti_sn65dsi86_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG,