net: stmmac: dwmac-qcom-ethqos: add support for emac4 on sa8775p platforms

sa8775p uses EMAC version 4, add the relevant defines, rename the
has_emac3 switch to has_emac_ge_3 (has emac greater-or-equal than 3)
and add the new compatible.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
index bdf59a179f87ebaee5e1ae69c778c759606c44e2..fa0fc53c56a311ffbe3821701ae367a7b83b0a3c 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
@@ -88,8 +88,9 @@ struct ethqos_emac_driver_data {
        const struct ethqos_emac_por *por;
        unsigned int num_por;
        bool rgmii_config_loopback_en;
-       bool has_emac3;
+       bool has_emac_ge_3;
        const char *link_clk_name;
+       bool has_integrated_pcs;
        struct dwmac4_addrs dwmac4_addrs;
 };
 
@@ -108,7 +109,7 @@ struct qcom_ethqos {
        const struct ethqos_emac_por *por;
        unsigned int num_por;
        bool rgmii_config_loopback_en;
-       bool has_emac3;
+       bool has_emac_ge_3;
 };
 
 static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset)
@@ -202,7 +203,7 @@ static const struct ethqos_emac_driver_data emac_v2_3_0_data = {
        .por = emac_v2_3_0_por,
        .num_por = ARRAY_SIZE(emac_v2_3_0_por),
        .rgmii_config_loopback_en = true,
-       .has_emac3 = false,
+       .has_emac_ge_3 = false,
 };
 
 static const struct ethqos_emac_por emac_v2_1_0_por[] = {
@@ -218,7 +219,7 @@ static const struct ethqos_emac_driver_data emac_v2_1_0_data = {
        .por = emac_v2_1_0_por,
        .num_por = ARRAY_SIZE(emac_v2_1_0_por),
        .rgmii_config_loopback_en = false,
-       .has_emac3 = false,
+       .has_emac_ge_3 = false,
 };
 
 static const struct ethqos_emac_por emac_v3_0_0_por[] = {
@@ -234,7 +235,41 @@ static const struct ethqos_emac_driver_data emac_v3_0_0_data = {
        .por = emac_v3_0_0_por,
        .num_por = ARRAY_SIZE(emac_v3_0_0_por),
        .rgmii_config_loopback_en = false,
-       .has_emac3 = true,
+       .has_emac_ge_3 = true,
+       .dwmac4_addrs = {
+               .dma_chan = 0x00008100,
+               .dma_chan_offset = 0x1000,
+               .mtl_chan = 0x00008000,
+               .mtl_chan_offset = 0x1000,
+               .mtl_ets_ctrl = 0x00008010,
+               .mtl_ets_ctrl_offset = 0x1000,
+               .mtl_txq_weight = 0x00008018,
+               .mtl_txq_weight_offset = 0x1000,
+               .mtl_send_slp_cred = 0x0000801c,
+               .mtl_send_slp_cred_offset = 0x1000,
+               .mtl_high_cred = 0x00008020,
+               .mtl_high_cred_offset = 0x1000,
+               .mtl_low_cred = 0x00008024,
+               .mtl_low_cred_offset = 0x1000,
+       },
+};
+
+static const struct ethqos_emac_por emac_v4_0_0_por[] = {
+       { .offset = RGMII_IO_MACRO_CONFIG,      .value = 0x40c01343 },
+       { .offset = SDCC_HC_REG_DLL_CONFIG,     .value = 0x2004642c },
+       { .offset = SDCC_HC_REG_DDR_CONFIG,     .value = 0x80040800 },
+       { .offset = SDCC_HC_REG_DLL_CONFIG2,    .value = 0x00200000 },
+       { .offset = SDCC_USR_CTL,               .value = 0x00010800 },
+       { .offset = RGMII_IO_MACRO_CONFIG2,     .value = 0x00002060 },
+};
+
+static const struct ethqos_emac_driver_data emac_v4_0_0_data = {
+       .por = emac_v4_0_0_por,
+       .num_por = ARRAY_SIZE(emac_v3_0_0_por),
+       .rgmii_config_loopback_en = false,
+       .has_emac_ge_3 = true,
+       .link_clk_name = "phyaux",
+       .has_integrated_pcs = true,
        .dwmac4_addrs = {
                .dma_chan = 0x00008100,
                .dma_chan_offset = 0x1000,
@@ -275,7 +310,7 @@ static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
        rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,
                      SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG);
 
-       if (!ethqos->has_emac3) {
+       if (!ethqos->has_emac_ge_3) {
                rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN,
                              0, SDCC_HC_REG_DLL_CONFIG);
 
@@ -316,7 +351,7 @@ static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
        rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN,
                      SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_HC_REG_DLL_CONFIG2);
 
-       if (!ethqos->has_emac3) {
+       if (!ethqos->has_emac_ge_3) {
                rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS,
                              0, SDCC_HC_REG_DLL_CONFIG2);
 
@@ -386,7 +421,7 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
                /* PRG_RCLK_DLY = TCXO period * TCXO_CYCLES_CNT / 2 * RX delay ns,
                 * in practice this becomes PRG_RCLK_DLY = 52 * 4 / 2 * RX delay ns
                 */
-               if (ethqos->has_emac3) {
+               if (ethqos->has_emac_ge_3) {
                        /* 0.9 ns */
                        rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,
                                      115, SDCC_HC_REG_DDR_CONFIG);
@@ -421,7 +456,7 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
                rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
                              0, RGMII_IO_MACRO_CONFIG2);
 
-               if (ethqos->has_emac3)
+               if (ethqos->has_emac_ge_3)
                        rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
                                      RGMII_CONFIG2_RX_PROG_SWAP,
                                      RGMII_IO_MACRO_CONFIG2);
@@ -461,7 +496,7 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
                              RGMII_IO_MACRO_CONFIG);
                rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
                              0, RGMII_IO_MACRO_CONFIG2);
-               if (ethqos->has_emac3)
+               if (ethqos->has_emac_ge_3)
                        rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
                                      RGMII_CONFIG2_RX_PROG_SWAP,
                                      RGMII_IO_MACRO_CONFIG2);
@@ -510,7 +545,7 @@ static int ethqos_configure_rgmii(struct qcom_ethqos *ethqos)
        rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN,
                      SDCC_DLL_CONFIG_PDN, SDCC_HC_REG_DLL_CONFIG);
 
-       if (ethqos->has_emac3) {
+       if (ethqos->has_emac_ge_3) {
                if (ethqos->speed == SPEED_1000) {
                        rgmii_writel(ethqos, 0x1800000, SDCC_TEST_CTL);
                        rgmii_writel(ethqos, 0x2C010800, SDCC_USR_CTL);
@@ -540,7 +575,7 @@ static int ethqos_configure_rgmii(struct qcom_ethqos *ethqos)
                              SDCC_HC_REG_DLL_CONFIG);
 
                /* Set USR_CTL bit 26 with mask of 3 bits */
-               if (!ethqos->has_emac3)
+               if (!ethqos->has_emac_ge_3)
                        rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26),
                                      SDCC_USR_CTL);
 
@@ -719,7 +754,7 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
        ethqos->por = data->por;
        ethqos->num_por = data->num_por;
        ethqos->rgmii_config_loopback_en = data->rgmii_config_loopback_en;
-       ethqos->has_emac3 = data->has_emac3;
+       ethqos->has_emac_ge_3 = data->has_emac_ge_3;
 
        ethqos->link_clk = devm_clk_get(dev, data->link_clk_name ?: "rgmii");
        if (IS_ERR(ethqos->link_clk)) {
@@ -749,12 +784,13 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
        plat_dat->fix_mac_speed = ethqos_fix_mac_speed;
        plat_dat->dump_debug_regs = rgmii_dump;
        plat_dat->has_gmac4 = 1;
-       if (ethqos->has_emac3)
+       if (ethqos->has_emac_ge_3)
                plat_dat->dwmac4_addrs = &data->dwmac4_addrs;
        plat_dat->pmt = 1;
        plat_dat->tso_en = of_property_read_bool(np, "snps,tso");
        if (of_device_is_compatible(np, "qcom,qcs404-ethqos"))
                plat_dat->rx_clk_runs_in_lpi = 1;
+       plat_dat->has_integrated_pcs = data->has_integrated_pcs;
 
        if (ethqos->serdes_phy) {
                plat_dat->serdes_powerup = qcom_ethqos_serdes_powerup;
@@ -775,6 +811,7 @@ out_config_dt:
 
 static const struct of_device_id qcom_ethqos_match[] = {
        { .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data},
+       { .compatible = "qcom,sa8775p-ethqos", .data = &emac_v4_0_0_data},
        { .compatible = "qcom,sc8280xp-ethqos", .data = &emac_v3_0_0_data},
        { .compatible = "qcom,sm8150-ethqos", .data = &emac_v2_1_0_data},
        { }