drm/xe: Do not spread i915_reg_defs.h include

Reduce the use of i915_reg_defs.h so it can be encapsulated in a single
place.

1) If it was being included by mistake, remove
2) If it was included for FIELD_GET()/FIELD_PREP()/GENMASK() and the
   like, just include <linux/bitfield.h>
3) If it was included to be able to define additional registers, move
   the registers to the relavant headers (regs/xe_regs.h or
   regs/xe_gt_regs.h)

v2:
  - Squash commit fixing i915_reg_defs.h include and with the one
    introducing regs/xe_reg_defs.h
  - Remove more cases of i915_reg_defs.h being used when all it was
    needed was linux/bitfield.h  (Matt Roper)
  - Move some  registers to the corresponding regs/*.h file (Matt Roper)

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
[Rodrigo squashed here the removal of the i915 include]

diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 58ee9e82156d3829a2aa4361ac7ec6457c459ed9..b3426f328d211b2daf1c61d594805fe0f2b8834a 100644 (file)
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -100,9 +100,6 @@ xe-y += xe_bb.o \
        xe_wa.o \
        xe_wopcm.o
 
-# XXX: Needed for i915 register definitions. Will be removed after xe-regs.
-subdir-ccflags-y += -I$(srctree)/drivers/gpu/drm/i915/
-
 obj-$(CONFIG_DRM_XE) += xe.o
 obj-$(CONFIG_DRM_XE_KUNIT_TEST) += tests/
 \

diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
index 6dfa3cf2fd43c296aee67842d3cd87b55ef383f1..2aa67d001c34b01af79c44592846b4f3a0a06971 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
@@ -8,7 +8,7 @@
 
 #include <asm/page.h>
 
-#include "i915_reg_defs.h"
+#include "regs/xe_reg_defs.h"
 
 #define RING_TAIL(base)                                _MMIO((base) + 0x30)
 

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index df2677c9c9f6dfea78aa64d8412a19adf0337f16..47377d2167e0ab8477bc29fbbe9ab09bef93eb5e 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -6,7 +6,7 @@
 #ifndef _XE_GT_REGS_H_
 #define _XE_GT_REGS_H_
 
-#include "i915_reg_defs.h"
+#include "regs/xe_reg_defs.h"
 
 /* RPM unit config (Gen8+) */
 #define RPM_CONFIG0                            _MMIO(0xd00)
@@ -108,6 +108,12 @@
 #define   GEN11_GT_VEBOX_DISABLE_SHIFT         16
 #define   GEN11_GT_VEBOX_DISABLE_MASK          (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT)
 
+#define XELP_EU_ENABLE                         _MMIO(0x9134)   /* "_DISABLE" on Xe_LP */
+#define   XELP_EU_MASK                         REG_GENMASK(7, 0)
+#define XELP_GT_GEOMETRY_DSS_ENABLE            _MMIO(0x913c)
+#define XEHP_GT_COMPUTE_DSS_ENABLE             _MMIO(0x9144)
+#define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT                _MMIO(0x9148)
+
 #define GEN6_GDRST                             _MMIO(0x941c)
 #define   GEN11_GRDOM_GUC                      REG_BIT(3)
 #define   GEN6_GRDOM_FULL                      (1 << 0)

diff --git a/drivers/gpu/drm/xe/regs/xe_reg_defs.h b/drivers/gpu/drm/xe/regs/xe_reg_defs.h
new file mode 100644 (file)
index 0000000..5f67356
--- /dev/null
+++ b/drivers/gpu/drm/xe/regs/xe_reg_defs.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef _XE_REG_DEFS_H_
+#define _XE_REG_DEFS_H_
+
+#include "../../i915/i915_reg_defs.h"
+
+#endif

diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
index a697162e1a77428353ac2f869d91da0ac524ad9b..2e7fbdedb5eb03adef911bc666990c547f7bcc2d 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_regs.h
@@ -5,7 +5,7 @@
 #ifndef _XE_REGS_H_
 #define _XE_REGS_H_
 
-#include "i915_reg_defs.h"
+#include "regs/xe_reg_defs.h"
 
 #define GU_CNTL                                        _MMIO(0x101010)
 #define   LMEM_INIT                            REG_BIT(7)
@@ -70,6 +70,8 @@
 #define PIPE_DSI0_OFFSET                       0x7b000
 #define PIPE_DSI1_OFFSET                       0x7b800
 
+#define SOFTWARE_FLAGS_SPR33                   _MMIO(0x4f084)
+
 #define GEN8_PCU_ISR                           _MMIO(0x444e0)
 #define GEN8_PCU_IMR                           _MMIO(0x444e4)
 #define GEN8_PCU_IIR                           _MMIO(0x444e8)

diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 6d7d57d08a997a86f1c14a309d397f3868300bea..00e8ed2353534f6b28f8cc8566951668b7dde4b4 100644 (file)
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -12,6 +12,7 @@
 #include <drm/drm_managed.h>
 #include <drm/xe_drm.h>
 
+#include "regs/xe_regs.h"
 #include "xe_bo.h"
 #include "xe_debugfs.h"
 #include "xe_dma_buf.h"
@@ -335,8 +336,6 @@ static void device_kill_persitent_engines(struct xe_device *xe,
        mutex_unlock(&xe->persitent_engines.lock);
 }
 
-#define SOFTWARE_FLAGS_SPR33         _MMIO(0x4F084)
-
 void xe_device_wmb(struct xe_device *xe)
 {
        struct xe_gt *gt = xe_device_get_gt(xe, 0);

diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.h b/drivers/gpu/drm/xe/xe_gt_mcr.h
index c31987d2177c9cfd7684fdef07b845b6ffae0875..2a6cd38c8cb758f2087aea732d2ce31bd2064c63 100644 (file)
--- a/drivers/gpu/drm/xe/xe_gt_mcr.h
+++ b/drivers/gpu/drm/xe/xe_gt_mcr.h
@@ -6,7 +6,7 @@
 #ifndef _XE_GT_MCR_H_
 #define _XE_GT_MCR_H_
 
-#include "i915_reg_defs.h"
+#include "regs/xe_reg_defs.h"
 
 struct drm_printer;
 struct xe_gt;

diff --git a/drivers/gpu/drm/xe/xe_gt_pagefault.c b/drivers/gpu/drm/xe/xe_gt_pagefault.c
index 0e7047b89a83c3840b225c5188eae6db3d70cd55..1677640e10753cb02738f0fb52b54034c499fda6 100644 (file)
--- a/drivers/gpu/drm/xe/xe_gt_pagefault.c
+++ b/drivers/gpu/drm/xe/xe_gt_pagefault.c
@@ -5,6 +5,7 @@
 
 #include "xe_gt_pagefault.h"
 
+#include <linux/bitfield.h>
 #include <linux/circ_buf.h>
 
 #include <drm/drm_managed.h>

diff --git a/drivers/gpu/drm/xe/xe_gt_topology.c b/drivers/gpu/drm/xe/xe_gt_topology.c
index c76aaea1887c3f10d77d2f348d2d454ae7769a18..2123f84be336e56b85ed6c1089b1e6ff8d592ecc 100644 (file)
--- a/drivers/gpu/drm/xe/xe_gt_topology.c
+++ b/drivers/gpu/drm/xe/xe_gt_topology.c
@@ -7,18 +7,13 @@
 
 #include <linux/bitmap.h>
 
+#include "regs/xe_gt_regs.h"
 #include "xe_gt.h"
 #include "xe_mmio.h"
 
 #define XE_MAX_DSS_FUSE_BITS (32 * XE_MAX_DSS_FUSE_REGS)
 #define XE_MAX_EU_FUSE_BITS (32 * XE_MAX_EU_FUSE_REGS)
 
-#define XELP_EU_ENABLE                         0x9134  /* "_DISABLE" on Xe_LP */
-#define   XELP_EU_MASK                         REG_GENMASK(7, 0)
-#define XELP_GT_GEOMETRY_DSS_ENABLE            0x913c
-#define XEHP_GT_COMPUTE_DSS_ENABLE             0x9144
-#define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT                0x9148
-
 static void
 load_dss_mask(struct xe_gt *gt, xe_dss_mask_t mask, int numregs, ...)
 {
@@ -41,7 +36,7 @@ static void
 load_eu_mask(struct xe_gt *gt, xe_eu_mask_t mask)
 {
        struct xe_device *xe = gt_to_xe(gt);
-       u32 reg = xe_mmio_read32(gt, XELP_EU_ENABLE);
+       u32 reg = xe_mmio_read32(gt, XELP_EU_ENABLE.reg);
        u32 val = 0;
        int i;
 
@@ -86,10 +81,10 @@ xe_gt_topology_init(struct xe_gt *gt)
        }
 
        load_dss_mask(gt, gt->fuse_topo.g_dss_mask, num_geometry_regs,
-                     XELP_GT_GEOMETRY_DSS_ENABLE);
+                     XELP_GT_GEOMETRY_DSS_ENABLE.reg);
        load_dss_mask(gt, gt->fuse_topo.c_dss_mask, num_compute_regs,
-                     XEHP_GT_COMPUTE_DSS_ENABLE,
-                     XEHPC_GT_COMPUTE_DSS_ENABLE_EXT);
+                     XEHP_GT_COMPUTE_DSS_ENABLE.reg,
+                     XEHPC_GT_COMPUTE_DSS_ENABLE_EXT.reg);
        load_eu_mask(gt, gt->fuse_topo.eu_mask_per_dss);
 
        xe_gt_topology_dump(gt, &p);

diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 661effa9830ff6c8fb55b5cde680a715f93f678b..58b9841616e4500e10b34717fd51498261cd1947 100644 (file)
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -22,14 +22,6 @@
 #include "xe_uc_fw.h"
 #include "xe_wopcm.h"
 
-#include "i915_reg_defs.h"
-
-/* TODO: move to common file */
-#define GUC_PVC_MOCS_INDEX_MASK                REG_GENMASK(25, 24)
-#define PVC_MOCS_UC_INDEX              1
-#define PVC_GUC_MOCS_INDEX(index)      REG_FIELD_PREP(GUC_PVC_MOCS_INDEX_MASK,\
-                                                      index)
-
 static struct xe_gt *
 guc_to_gt(struct xe_guc *guc)
 {

diff --git a/drivers/gpu/drm/xe/xe_guc_reg.h b/drivers/gpu/drm/xe/xe_guc_reg.h
index 513a7e0c8a5aae34b9e56b483c9d5444ce477e9d..efd60c186bbc0abd42e30c8d01a374d9c11155af 100644 (file)
--- a/drivers/gpu/drm/xe/xe_guc_reg.h
+++ b/drivers/gpu/drm/xe/xe_guc_reg.h
@@ -9,7 +9,7 @@
 #include <linux/compiler.h>
 #include <linux/types.h>
 
-#include "i915_reg_defs.h"
+#include "regs/xe_reg_defs.h"
 
 /* Definitions of GuC H/W registers, bits, etc */
 
@@ -93,6 +93,10 @@
 #define   GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA (1<<10)
 #define   GUC_ENABLE_MIA_CLOCK_GATING          (1<<15)
 #define   GUC_GEN10_SHIM_WC_ENABLE             (1<<21)
+#define   PVC_GUC_MOCS_INDEX_MASK              REG_GENMASK(25, 24)
+#define   PVC_MOCS_UC_INDEX                    1
+#define   PVC_GUC_MOCS_INDEX(index)            REG_FIELD_PREP(PVC_GUC_MOCS_INDEX_MASK,\
+                                                              index)
 
 #define GUC_SEND_INTERRUPT             _MMIO(0xc4c8)
 #define   GUC_SEND_TRIGGER               (1<<0)

diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index e2ee51381ac1b0d51ad6a9ffebea32eaf80816d8..79aa3508ae3e7cf4bd693358f9784495189d9002 100644 (file)
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -5,6 +5,7 @@
 
 #include "xe_migrate.h"
 
+#include <linux/bitfield.h>
 #include <linux/sizes.h>
 
 #include <drm/drm_managed.h>

diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h b/drivers/gpu/drm/xe/xe_pcode_api.h
index 0762c8a912c798b1577e7a4fb386918d09497ef9..4e689cd4b23b86875bbed05a14029ce70c0a1106 100644 (file)
--- a/drivers/gpu/drm/xe/xe_pcode_api.h
+++ b/drivers/gpu/drm/xe/xe_pcode_api.h
@@ -5,6 +5,8 @@
 
 /* Internal to xe_pcode */
 
+#include "regs/xe_reg_defs.h"
+
 #define PCODE_MAILBOX                  _MMIO(0x138124)
 #define   PCODE_READY                  REG_BIT(31)
 #define   PCODE_MB_PARAM2              REG_GENMASK(23, 16)

diff --git a/drivers/gpu/drm/xe/xe_reg_sr_types.h b/drivers/gpu/drm/xe/xe_reg_sr_types.h
index b234a8673e54b193d3e6c55932c9d126ba778cfd..0e6d542ff1b4ea444ef3711139d45ab6ea24a912 100644 (file)
--- a/drivers/gpu/drm/xe/xe_reg_sr_types.h
+++ b/drivers/gpu/drm/xe/xe_reg_sr_types.h
@@ -9,8 +9,6 @@
 #include <linux/types.h>
 #include <linux/xarray.h>
 
-#include "i915_reg_defs.h"
-
 struct xe_reg_sr_entry {
        u32             clr_bits;
        u32             set_bits;

diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
index d6ba0b7e5042eb3ef726a9b8347c6ae26de43ecc..bd44fd8bbe0573f27a4c738e0b0c0de0e784f5d6 100644 (file)
--- a/drivers/gpu/drm/xe/xe_rtp.h
+++ b/drivers/gpu/drm/xe/xe_rtp.h
@@ -11,8 +11,6 @@
 
 #include "xe_rtp_types.h"
 
-#include "i915_reg_defs.h"
-
 /*
  * Register table poke infrastructure
  */

diff --git a/drivers/gpu/drm/xe/xe_rtp_types.h b/drivers/gpu/drm/xe/xe_rtp_types.h
index fac0bd6d5b1e01f328a788301c36cd42b89da210..e87f1b280d968aed04dcafefc2f6c9c4eebc76bd 100644 (file)
--- a/drivers/gpu/drm/xe/xe_rtp_types.h
+++ b/drivers/gpu/drm/xe/xe_rtp_types.h
@@ -8,8 +8,6 @@
 
 #include <linux/types.h>
 
-#include "i915_reg_defs.h"
-
 struct xe_hw_engine;
 struct xe_gt;
 

diff --git a/drivers/gpu/drm/xe/xe_step.c b/drivers/gpu/drm/xe/xe_step.c
index ca77d0971529761316015b0a605d3b359fffa386..14f482f29ae447c325195177f2b726b368a50926 100644 (file)
--- a/drivers/gpu/drm/xe/xe_step.c
+++ b/drivers/gpu/drm/xe/xe_step.c
@@ -5,6 +5,8 @@
 
 #include "xe_step.h"
 
+#include <linux/bitfield.h>
+
 #include "xe_device.h"
 #include "xe_platform_types.h"