drm/xe: Add missing DG2 lrc workarounds

Synchronize with i915 the DG2 lrc workarounds as of
commit 4d14d7717f19 ("drm/i915/selftest: Fix ktime_get() and h/w access
order").

A few simplifications were done when the WA should be applied to some
steps of a subplatform and all the steppings of the other subplatforms.
In this case, it was simply applied to all the steppings, which only
means applying it to a few more A* steppings.

The implementation of the workaround 16011186671 triggers a bug in the
RTP infra: it's not possible to set the flag the usual way when having
multiple actions in the entry. This may be fixed later, but for now it's
sufficient to just set the flag directly without the helper macro.

v2: Fix 14014947963 to use FIELD_SET (Matt Roper)

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230314003012.2600353-12-lucas.demarchi@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 97a9d78e883144dcf77c2bbf0f77973034fa29cf..a079e1aef5a488c55c923911f2f9c09ba3903ed3 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -73,9 +73,16 @@
 #define XEHP_TILE0_ADDR_RANGE                  MCR_REG(0x4900)
 #define XEHP_FLAT_CCS_BASE_ADDR                        MCR_REG(0x4910)
 
+#define CHICKEN_RASTER_1                       MCR_REG(0x6204)
+#define   DIS_SF_ROUND_NEAREST_EVEN            REG_BIT(8)
+
 #define CHICKEN_RASTER_2                       MCR_REG(0x6208)
 #define   TBIMR_FAST_CLIP                      REG_BIT(5)
 
+#define VFLSKPD                                        MCR_REG(0x62a8)
+#define   DIS_OVER_FETCH_CACHE                 REG_BIT(1)
+#define   DIS_MULT_MISS_RD_SQUASH              REG_BIT(0)
+
 #define GEN12_FF_MODE2                         _MMIO(0x6604)
 #define XEHP_FF_MODE2                          MCR_REG(0x6604)
 #define   FF_MODE2_GS_TIMER_MASK               REG_GENMASK(31, 24)
@@ -83,6 +90,12 @@
 #define   FF_MODE2_TDS_TIMER_MASK              REG_GENMASK(23, 16)
 #define   FF_MODE2_TDS_TIMER_128               REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
 
+#define CACHE_MODE_1                           _MMIO(0x7004)
+#define   MSAA_OPTIMIZATION_REDUC_DISABLE      REG_BIT(11)
+
+#define XEHP_PSS_MODE2                         MCR_REG(0x703c)
+#define   SCOREBOARD_STALL_FLUSH_CONTROL       REG_BIT(5)
+
 #define HIZ_CHICKEN                            _MMIO(0x7018)
 #define   DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE REG_BIT(14)
 
@@ -96,6 +109,12 @@
 #define   GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC   REG_BIT(11)
 #define   GEN12_DISABLE_CPS_AWARE_COLOR_PIPE   REG_BIT(9)
 
+#define XEHP_SLICE_COMMON_ECO_CHICKEN1         MCR_REG(0x731c)
+#define   MSC_MSAA_REODER_BUF_BYPASS_DISABLE   REG_BIT(14)
+
+#define VF_PREEMPTION                          _MMIO(0x83a4)
+#define   PREEMPTION_VERTEX_COUNT              REG_GENMASK(15, 0)
+
 #define VFG_PREEMPTION_CHICKEN                 _MMIO(0x83b4)
 #define   POLYGON_TRIFAN_LINELOOP_DISABLE      REG_BIT(4)
 

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 306541b229bf10c9c2ad9622f7a04847ae3442c3..0621706f46e6242a4863d7902bd408b602cdb949 100644 (file)
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -541,6 +541,57 @@ static const struct xe_rtp_entry lrc_was[] = {
                             DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE,
                             XE_RTP_ACTION_FLAG(MASKED_REG)))
        },
+
+       /* DG2 */
+
+       { XE_RTP_NAME("16011186671"),
+         XE_RTP_RULES(SUBPLATFORM(DG2, G11), STEP(A0, B0)),
+         XE_RTP_ACTIONS(CLR(VFLSKPD, DIS_MULT_MISS_RD_SQUASH,
+                            .flags = XE_RTP_ACTION_FLAG_MASKED_REG),
+                        SET(VFLSKPD, DIS_OVER_FETCH_CACHE,
+                            .flags = XE_RTP_ACTION_FLAG_MASKED_REG))
+       },
+       { XE_RTP_NAME("14010469329"),
+         XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0)),
+         XE_RTP_ACTIONS(SET(XEHP_COMMON_SLICE_CHICKEN3,
+                            XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE,
+                            XE_RTP_ACTION_FLAG(MASKED_REG)))
+       },
+       { XE_RTP_NAME("14010698770, 22010613112, 22010465075"),
+         XE_RTP_RULES(SUBPLATFORM(DG2, G10), STEP(A0, B0)),
+         XE_RTP_ACTIONS(SET(XEHP_COMMON_SLICE_CHICKEN3,
+                            GEN12_DISABLE_CPS_AWARE_COLOR_PIPE,
+                            XE_RTP_ACTION_FLAG(MASKED_REG)))
+       },
+       { XE_RTP_NAME("16013271637"),
+         XE_RTP_RULES(PLATFORM(DG2)),
+         XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1,
+                            MSC_MSAA_REODER_BUF_BYPASS_DISABLE,
+                            XE_RTP_ACTION_FLAG(MASKED_REG)))
+       },
+       { XE_RTP_NAME("14014947963"),
+         XE_RTP_RULES(PLATFORM(DG2)),
+         XE_RTP_ACTIONS(FIELD_SET(VF_PREEMPTION,
+                                  PREEMPTION_VERTEX_COUNT,
+                                  0x4000,
+                                  XE_RTP_ACTION_FLAG(MASKED_REG)))
+       },
+       { XE_RTP_NAME("18018764978"),
+         XE_RTP_RULES(PLATFORM(DG2)),
+         XE_RTP_ACTIONS(SET(XEHP_PSS_MODE2,
+                            SCOREBOARD_STALL_FLUSH_CONTROL,
+                            XE_RTP_ACTION_FLAG(MASKED_REG)))
+       },
+       { XE_RTP_NAME("15010599737"),
+         XE_RTP_RULES(PLATFORM(DG2)),
+         XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN,
+                            XE_RTP_ACTION_FLAG(MASKED_REG)))
+       },
+       { XE_RTP_NAME("18019271663"),
+         XE_RTP_RULES(PLATFORM(DG2)),
+         XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE,
+                            XE_RTP_ACTION_FLAG(MASKED_REG)))
+       },
        {}
 };