drm/amd/display: Fix MST recognizes connected displays as one

MST now recognizes both connected displays

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Muhammad Ahmed <ahmed.ahmed@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c
index 70a66df8315abf3f1d2e3b821d2b0d02c7d50dfa..22137fde62bdb471f2708d0d271ae524961113e8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c
@@ -635,8 +635,55 @@ static void dccg35_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst,
        }
 }
 
+/*get other front end connected to this backend*/
+static uint8_t dccg35_get_other_enabled_symclk_fe(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)
+{
+       uint8_t num_enabled_symclk_fe = 0;
+       uint32_t be_clk_en = 0, fe_clk_en[5] = {0}, be_clk_sel[5] = {0};
+       struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+       switch (link_enc_inst) {
+       case 0:
+               REG_GET_3(SYMCLKA_CLOCK_ENABLE, SYMCLKA_CLOCK_ENABLE, &be_clk_en,
+                               SYMCLKA_FE_EN, &fe_clk_en[0],
+                               SYMCLKA_FE_SRC_SEL, &be_clk_sel[0]);
+                               break;
+       case 1:
+               REG_GET_3(SYMCLKB_CLOCK_ENABLE, SYMCLKB_CLOCK_ENABLE, &be_clk_en,
+                               SYMCLKB_FE_EN, &fe_clk_en[1],
+                               SYMCLKB_FE_SRC_SEL, &be_clk_sel[1]);
+                               break;
+       case 2:
+                       REG_GET_3(SYMCLKC_CLOCK_ENABLE, SYMCLKC_CLOCK_ENABLE, &be_clk_en,
+                               SYMCLKC_FE_EN, &fe_clk_en[2],
+                               SYMCLKC_FE_SRC_SEL, &be_clk_sel[2]);
+                               break;
+       case 3:
+                       REG_GET_3(SYMCLKD_CLOCK_ENABLE, SYMCLKD_CLOCK_ENABLE, &be_clk_en,
+                               SYMCLKD_FE_EN, &fe_clk_en[3],
+                               SYMCLKD_FE_SRC_SEL, &be_clk_sel[3]);
+                               break;
+       case 4:
+                       REG_GET_3(SYMCLKE_CLOCK_ENABLE, SYMCLKE_CLOCK_ENABLE, &be_clk_en,
+                               SYMCLKE_FE_EN, &fe_clk_en[4],
+                               SYMCLKE_FE_SRC_SEL, &be_clk_sel[4]);
+                               break;
+       }
+       if (be_clk_en) {
+       /* for DPMST, this backend could be used by multiple front end.
+       only disable the backend if this stream_enc_ins is the last active stream enc connected to this back_end*/
+               uint8_t i;
+               for (i = 0; i != link_enc_inst && i < sizeof(fe_clk_en); i++) {
+                       if (fe_clk_en[i] && be_clk_sel[i] == link_enc_inst)
+                               num_enabled_symclk_fe++;
+               }
+       }
+       return num_enabled_symclk_fe;
+}
+
 static void dccg35_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)
 {
+       uint8_t num_enabled_symclk_fe = 0;
        struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
 
        switch (stream_enc_inst) {
@@ -667,27 +714,33 @@ static void dccg35_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst
                break;
        }
 
-       switch (link_enc_inst) {
-       case 0:
-               REG_UPDATE(SYMCLKA_CLOCK_ENABLE,
-                               SYMCLKA_CLOCK_ENABLE, 0);
-               break;
-       case 1:
-               REG_UPDATE(SYMCLKB_CLOCK_ENABLE,
-                               SYMCLKB_CLOCK_ENABLE, 0);
-               break;
-       case 2:
-               REG_UPDATE(SYMCLKC_CLOCK_ENABLE,
-                               SYMCLKC_CLOCK_ENABLE, 0);
-               break;
-       case 3:
-               REG_UPDATE(SYMCLKD_CLOCK_ENABLE,
-                               SYMCLKD_CLOCK_ENABLE, 0);
-               break;
-       case 4:
-               REG_UPDATE(SYMCLKE_CLOCK_ENABLE,
-                               SYMCLKE_CLOCK_ENABLE, 0);
-               break;
+       /*check other enabled symclk fe */
+       num_enabled_symclk_fe = dccg35_get_other_enabled_symclk_fe(dccg, stream_enc_inst, link_enc_inst);
+       /*only turn off backend clk if other front end attachecd to this backend are all off,
+        for mst, only turn off the backend if this is the last front end*/
+       if (num_enabled_symclk_fe == 0) {
+               switch (link_enc_inst) {
+               case 0:
+                       REG_UPDATE(SYMCLKA_CLOCK_ENABLE,
+                                       SYMCLKA_CLOCK_ENABLE, 0);
+                       break;
+               case 1:
+                       REG_UPDATE(SYMCLKB_CLOCK_ENABLE,
+                                       SYMCLKB_CLOCK_ENABLE, 0);
+                       break;
+               case 2:
+                       REG_UPDATE(SYMCLKC_CLOCK_ENABLE,
+                                       SYMCLKC_CLOCK_ENABLE, 0);
+                       break;
+               case 3:
+                       REG_UPDATE(SYMCLKD_CLOCK_ENABLE,
+                                       SYMCLKD_CLOCK_ENABLE, 0);
+                       break;
+               case 4:
+                       REG_UPDATE(SYMCLKE_CLOCK_ENABLE,
+                                       SYMCLKE_CLOCK_ENABLE, 0);
+                       break;
+               }
        }
 }
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
index 7fa1172b98d0765d088db25123e2439517f6df12..4a0bca1345811b4715cd994b586b9721a726e2ab 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
@@ -751,14 +751,10 @@ static const struct dc_debug_options debug_defaults_drv = {
        .disable_unbounded_requesting = false,
        .disable_mem_low_power = true,
        .enable_hpo_pg_support = false,
-
        //must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions
        .enable_double_buffered_dsc_pg_support = false,
        .enable_dp_dig_pixel_rate_div_policy = 1,
-       .disable_stutter = true,
-       .disable_idle_power_optimizations = true,
        .disable_z10 = false,
-       .disable_mem_low_power = true,
        .ignore_pg = true,
        .psp_disabled_wa = true,
        .disable_ips = true,