riscv: dts: starfive: jh7110: Add PWM node and pins configuration

Add OpenCores PWM controller node and add PWM pins configuration
on VisionFive 2 board.

Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index b89e9791efa72a2a0bf1393d8c97d5043a9a024f..e08af8a830abf85b0bb789cdf67475bc026f4fa3 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -323,6 +323,12 @@
        };
 };
 
+&pwm {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pwm_pins>;
+       status = "okay";
+};
+
 &spi0 {
        pinctrl-names = "default";
        pinctrl-0 = <&spi0_pins>;
@@ -513,6 +519,22 @@
                };
        };
 
+       pwm_pins: pwm-0 {
+               pwm-pins {
+                       pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0,
+                                             GPOEN_SYS_PWM0_CHANNEL0,
+                                             GPI_NONE)>,
+                                <GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1,
+                                             GPOEN_SYS_PWM0_CHANNEL1,
+                                             GPI_NONE)>;
+                       bias-disable;
+                       drive-strength = <12>;
+                       input-disable;
+                       input-schmitt-disable;
+                       slew-rate = <0>;
+               };
+       };
+
        spi0_pins: spi0-0 {
                mosi-pins {
                        pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 45213cdf50dc75a9fa6610710a4d0cbe58b44c51..1b782f2c13956fb64bca473a3541984e89b4a17a 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -829,6 +829,15 @@
                        status = "disabled";
                };
 
+               pwm: pwm@120d0000 {
+                       compatible = "starfive,jh7110-pwm", "opencores,pwm-v1";
+                       reg = <0x0 0x120d0000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_PWM_APB>;
+                       resets = <&syscrg JH7110_SYSRST_PWM_APB>;
+                       #pwm-cells = <3>;
+                       status = "disabled";
+               };
+
                sfctemp: temperature-sensor@120e0000 {
                        compatible = "starfive,jh7110-temp";
                        reg = <0x0 0x120e0000 0x0 0x10000>;