arm64: dts: renesas: r9a07g054: Fillup the sbc stub node

Fillup the sbc stub node in RZ/V2L (R9A07G054) SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220227203744.18355-7-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index fafb986fe3bcca53fbedbeae4f2b0b9e8c31ee69..1207a99bf3fede529da8c581c6dd4cc1f9cdbfb1 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -398,12 +398,20 @@
                };
 
                sbc: spi@10060000 {
+                       compatible = "renesas,r9a07g054-rpc-if",
+                                    "renesas,rzg2l-rpc-if";
                        reg = <0 0x10060000 0 0x10000>,
                              <0 0x20000000 0 0x10000000>,
                              <0 0x10070000 0 0x10000>;
+                       reg-names = "regs", "dirmap", "wbuf";
+                       interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD R9A07G054_SPI_CLK2>,
+                                <&cpg CPG_MOD R9A07G054_SPI_CLK>;
+                       resets = <&cpg R9A07G054_SPI_RST>;
+                       power-domains = <&cpg>;
                        #address-cells = <1>;
                        #size-cells = <0>;
-                       /* place holder */
+                       status = "disabled";
                };
 
                cpg: clock-controller@11010000 {