phy: qcom-qmp: pcs-usb: Add v7 register offsets

The X1E80100 platform bumps the HW version of QMP phy to v7 for USB.
Add the new PCS USB specific offsets in a dedicated header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-4-dfd1c375ef61@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v7.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v7.h
new file mode 100644 (file)
index 0000000..24368d4
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v7.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_USB_V7_H_
+#define QCOM_PHY_QMP_PCS_USB_V7_H_
+
+#define QPHY_V7_PCS_USB3_POWER_STATE_CONFIG1           0x00
+#define QPHY_V7_PCS_USB3_AUTONOMOUS_MODE_CTRL          0x08
+#define QPHY_V7_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR         0x14
+#define QPHY_V7_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL       0x18
+#define QPHY_V7_PCS_USB3_RXEQTRAINING_DFE_TIME_S2      0x3c
+#define QPHY_V7_PCS_USB3_RCVR_DTCT_DLY_U3_L            0x40
+#define QPHY_V7_PCS_USB3_RCVR_DTCT_DLY_U3_H            0x44
+
+#endif